From 3f4af0da938e0d9f4d80e77a3d8abd1f6400e57e Mon Sep 17 00:00:00 2001 From: Meera Ravindranath Date: Wed, 12 Feb 2020 16:01:22 +0530 Subject: soc/intel/common: Update Jasper Lake Device IDs Update Jasper Lake CPU, SA and PCH IDs. BUG=b:149185282 BRANCH=None TEST=Compilation for Jasper Lake board is working Change-Id: I2c9ec1eb4236184b981d99250f263172c82f7117 Signed-off-by: Meera Ravindranath Signed-off-by: Varshit Pandya Reviewed-on: https://review.coreboot.org/c/coreboot/+/38849 Tested-by: build bot (Jenkins) Reviewed-by: Aamir Bohra Reviewed-by: Wonkyu Kim --- src/soc/intel/common/block/pcie/pcie.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'src/soc/intel/common/block/pcie/pcie.c') diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index eab6667b7f..cc20a48d22 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -290,14 +290,6 @@ static const unsigned short pcie_device_ids[] = { PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP14, PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP15, PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP16, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP1, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP2, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP3, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP4, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP5, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP6, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP7, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP8, PCI_DEVICE_ID_INTEL_MCC_PCIE_RP1, PCI_DEVICE_ID_INTEL_MCC_PCIE_RP2, PCI_DEVICE_ID_INTEL_MCC_PCIE_RP3, @@ -305,6 +297,14 @@ static const unsigned short pcie_device_ids[] = { PCI_DEVICE_ID_INTEL_MCC_PCIE_RP5, PCI_DEVICE_ID_INTEL_MCC_PCIE_RP6, PCI_DEVICE_ID_INTEL_MCC_PCIE_RP7, + PCI_DEVICE_ID_INTEL_JSP_PCIE_RP1, + PCI_DEVICE_ID_INTEL_JSP_PCIE_RP2, + PCI_DEVICE_ID_INTEL_JSP_PCIE_RP3, + PCI_DEVICE_ID_INTEL_JSP_PCIE_RP4, + PCI_DEVICE_ID_INTEL_JSP_PCIE_RP5, + PCI_DEVICE_ID_INTEL_JSP_PCIE_RP6, + PCI_DEVICE_ID_INTEL_JSP_PCIE_RP7, + PCI_DEVICE_ID_INTEL_JSP_PCIE_RP8, 0 }; -- cgit v1.2.3