From 26136092c01b8d29fde68058597b74923c21a41f Mon Sep 17 00:00:00 2001 From: "Tan, Lean Sheng" Date: Mon, 20 Jan 2020 19:13:56 -0800 Subject: soc/intel/common: Add Elkhartlake Device IDs Add Elkhartlake CPU, SA and PCH IDs. EHL PCH is code named as MCC. Also add a MCH ID (JSL_EHL) which is shared by both JSL and EHL SKUs. Signed-off-by: Lean Sheng Tan Change-Id: I03f15832143bcc3095a3936c65fbc30a95e7f0f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38489 Reviewed-by: Subrata Banik Reviewed-by: Ronak Kanabar Reviewed-by: Werner Zeh Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/pcie/pcie.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'src/soc/intel/common/block/pcie/pcie.c') diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index ce43d3400e..eab6667b7f 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -298,6 +298,13 @@ static const unsigned short pcie_device_ids[] = { PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP6, PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP7, PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP8, + PCI_DEVICE_ID_INTEL_MCC_PCIE_RP1, + PCI_DEVICE_ID_INTEL_MCC_PCIE_RP2, + PCI_DEVICE_ID_INTEL_MCC_PCIE_RP3, + PCI_DEVICE_ID_INTEL_MCC_PCIE_RP4, + PCI_DEVICE_ID_INTEL_MCC_PCIE_RP5, + PCI_DEVICE_ID_INTEL_MCC_PCIE_RP6, + PCI_DEVICE_ID_INTEL_MCC_PCIE_RP7, 0 }; -- cgit v1.2.3