From 64bc26ad1553eec6bbbd6deac21a3e79ca7ce455 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Sat, 10 Oct 2020 00:15:28 +0000 Subject: soc/intel/common: Add PCIe Runtime D3 driver for ACPI This driver is for devices attached to a PCIe root port that support Runtime D3. It creates the necessary PowerResource in the root port to provide _ON/_OFF methods for which will turn off power and clocks to the device when it is in the D3cold state. The mainboard declares the driver in devicetree and provides the GPIOs that control power/reset for the device attached to the root port and the SRCCLK pin used for the PMC IPC mailbox to enable/disable the clock. An additional device property is created for storage devices if it matches the PCI storage class which is used to indicate that the storage device should use D3 for power savings. BUG=b:160996445 TEST=boot on volteer device with this driver enabled in the devicetree and disassemble the SSDT to ensure this code exists. Signed-off-by: Duncan Laurie Change-Id: I13e59c996b4f5e4c2657694bda9fad869b64ffde Reviewed-on: https://review.coreboot.org/c/coreboot/+/46260 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/common/block/pcie/Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/soc/intel/common/block/pcie/Makefile.inc') diff --git a/src/soc/intel/common/block/pcie/Makefile.inc b/src/soc/intel/common/block/pcie/Makefile.inc index 0cded9dce7..e2ad685bc3 100644 --- a/src/soc/intel/common/block/pcie/Makefile.inc +++ b/src/soc/intel/common/block/pcie/Makefile.inc @@ -1,2 +1,4 @@ +subdirs-y += ./* + ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE) += pcie.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE) += pcie_rp.c -- cgit v1.2.3