From de2ab41fc43152b652af7c1f658b1c27926afd6c Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Mon, 11 Jan 2021 16:14:14 +0800 Subject: soc/intel/common: Move L1_substates_control to pcie_rp.h L1_substates_control is common define. Move out of soc level. Signed-off-by: Eric Lai Change-Id: I54574b606985e82d00beb1a61cce3097580366a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49295 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Furquan Shaikh --- src/soc/intel/common/block/include/intelblocks/pcie_rp.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/soc/intel/common/block/include') diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h index 578a600e5b..2030e72453 100644 --- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h +++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h @@ -63,4 +63,12 @@ void pcie_rp_update_devicetree(const struct pcie_rp_group *groups); */ uint32_t pcie_rp_enable_mask(const struct pcie_rp_group *groups); +/* This enum is for passing into an FSP UPD, typically PcieRpL1Substates */ +enum L1_substates_control { + L1_SS_FSP_DEFAULT, + L1_SS_DISABLED, + L1_SS_L1_1, + L1_SS_L1_2, +}; + #endif /* SOC_INTEL_COMMON_BLOCK_PCIE_RP_H */ -- cgit v1.2.3