From 7d68353d154d17b1f70f7724f537305c782aa54a Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 19 Jan 2023 23:11:43 +0530 Subject: =?UTF-8?q?soc/intel/cmn/pmc:=20Create=20API=20to=20clear=20PMC=20?= =?UTF-8?q?power=20failure=C2=A0status=20bits?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch implements an API named `pmc_clear_pmcon_pwr_failure_sts()` to clear power failure status bits of PMC General PM Configuration A/B based on the underlying SoC. Based on the available PMC register definitions between Sky Lake till latest Meteor Lake platform, the SoC platform that selects SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION config has power failure bits mapped into the MMIO mapped GEN_PMCON_A register where else for the other SoCs, those power failure bits are belongs to the PCI config space mapped GEN_PMCON_B register. BUG=b:265939425 TEST=Able to build the google/marasov. Signed-off-by: Subrata Banik Change-Id: Icbbe47ccfd489edf9c38f52bdf7cf2de7aa9eedf Reviewed-on: https://review.coreboot.org/c/coreboot/+/72053 Reviewed-by: Kapil Porwal Tested-by: build bot (Jenkins) Reviewed-by: Lean Sheng Tan Reviewed-by: Sridhar Siricilla --- src/soc/intel/common/block/include/intelblocks/pmclib.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/soc/intel/common/block/include') diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h index 36049ba48a..11ab86d47a 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmclib.h +++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h @@ -183,6 +183,9 @@ int pmc_fill_power_state(struct chipset_power_state *ps); */ void pmc_gpe_init(void); +/* Clear PMC GEN_PMCON_X register power failure status bits */ +void pmc_clear_pmcon_pwr_failure_sts(void); + /* Clear PMC GEN_PMCON_A register status bits */ void pmc_clear_pmcon_sts(void); -- cgit v1.2.3