From 4b8092aebbcf2316a0b34d340f18bf7d4ae02ed5 Mon Sep 17 00:00:00 2001 From: Jamie Ryu Date: Tue, 2 Aug 2022 09:14:23 -0700 Subject: soc/intel/common/gpio: Support 4 bits GPIO pad mode configuration Intel GPIO pad supports 4 bits pad mode, PAD_CFG_DW0[13:10] for pins that native function 8 to 15 is assigned. This adds native function definitions from NF8 to NF15 and updates PAD_CFG0_MODE_MASK to support 4 bits pad mode configuration. Since PAD_CFG_DW0[16:13] is reserved for pins that NF8 or higher is not assigned, this change would not cause an issue but Kconfig option is added to minimize an impact and support 4 bits pad mode configuration. BUG=b:239690757 TEST=build and verify pad mode configuration with Meteor Lake mtlrvp Signed-off-by: Jamie Ryu Change-Id: Iefd2daa92a86402f2154de2a013ea30f95d98108 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66375 Tested-by: build bot (Jenkins) Reviewed-by: Tarun Tuli Reviewed-by: Eric Lai Reviewed-by: Subrata Banik --- .../common/block/include/intelblocks/gpio_defs.h | 37 ++++++++++++++++------ 1 file changed, 27 insertions(+), 10 deletions(-) (limited to 'src/soc/intel/common/block/include') diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index beff0a0f9b..3790ba41d8 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -5,6 +5,8 @@ #include +#define _BIT_WIDTH(x) ((1 << (x)) - 1) + #define PAD_CFG0_TX_STATE_BIT 0 #define PAD_CFG0_TX_STATE (1 << PAD_CFG0_TX_STATE_BIT) #define PAD_CFG0_RX_STATE_BIT 1 @@ -12,16 +14,31 @@ #define PAD_CFG0_TX_DISABLE (1 << 8) #define PAD_CFG0_RX_DISABLE (1 << 9) #define PAD_CFG0_MODE_SHIFT 10 -#define PAD_CFG0_MODE_MASK (7 << 10) -#define PAD_CFG0_MODE_GPIO (0 << 10) -#define PAD_CFG0_MODE_FUNC(x) ((x) << 10) -#define PAD_CFG0_MODE_NF1 (1 << 10) -#define PAD_CFG0_MODE_NF2 (2 << 10) -#define PAD_CFG0_MODE_NF3 (3 << 10) -#define PAD_CFG0_MODE_NF4 (4 << 10) -#define PAD_CFG0_MODE_NF5 (5 << 10) -#define PAD_CFG0_MODE_NF6 (6 << 10) -#define PAD_CFG0_MODE_NF7 (7 << 10) +#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PMODE_4BITS) +#define PAD_CFG0_MODE_BIT_WIDTH _BIT_WIDTH(4) +#else +#define PAD_CFG0_MODE_BIT_WIDTH _BIT_WIDTH(3) +#endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PMODE_4BITS */ +#define PAD_CFG0_MODE_MASK (PAD_CFG0_MODE_BIT_WIDTH << PAD_CFG0_MODE_SHIFT) +#define PAD_CFG0_MODE_FUNC(x) ((x) << PAD_CFG0_MODE_SHIFT) +#define PAD_CFG0_MODE_GPIO PAD_CFG0_MODE_FUNC(0) +#define PAD_CFG0_MODE_NF1 PAD_CFG0_MODE_FUNC(1) +#define PAD_CFG0_MODE_NF2 PAD_CFG0_MODE_FUNC(2) +#define PAD_CFG0_MODE_NF3 PAD_CFG0_MODE_FUNC(3) +#define PAD_CFG0_MODE_NF4 PAD_CFG0_MODE_FUNC(4) +#define PAD_CFG0_MODE_NF5 PAD_CFG0_MODE_FUNC(5) +#define PAD_CFG0_MODE_NF6 PAD_CFG0_MODE_FUNC(6) +#define PAD_CFG0_MODE_NF7 PAD_CFG0_MODE_FUNC(7) +#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PMODE_4BITS) +#define PAD_CFG0_MODE_NF8 PAD_CFG0_MODE_FUNC(8) +#define PAD_CFG0_MODE_NF9 PAD_CFG0_MODE_FUNC(9) +#define PAD_CFG0_MODE_NF10 PAD_CFG0_MODE_FUNC(10) +#define PAD_CFG0_MODE_NF11 PAD_CFG0_MODE_FUNC(11) +#define PAD_CFG0_MODE_NF12 PAD_CFG0_MODE_FUNC(12) +#define PAD_CFG0_MODE_NF13 PAD_CFG0_MODE_FUNC(13) +#define PAD_CFG0_MODE_NF14 PAD_CFG0_MODE_FUNC(14) +#define PAD_CFG0_MODE_NF15 PAD_CFG0_MODE_FUNC(15) +#endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PMODE_4BITS */ #define PAD_CFG0_ROUTE_MASK (0xF << 17) #define PAD_CFG0_ROUTE_NMI (1 << 17) #define PAD_CFG0_ROUTE_SMI (1 << 18) -- cgit v1.2.3