From 310c7637daba6ba4e9249928e5cd0e45ef4661e1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Thu, 1 Oct 2020 22:28:03 +0200 Subject: soc/intel: deduplicate ACPI timer emulation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The code for enabling ACPI timer emulation is the same for the SoCs SKL, CNL, ICL, TGL, JSL and EHL. Deduplicate it by moving it to common code. APL differs in not having the delay settings. However, the bits are marked as "spare" and BWG mentions there are no "reserved bit checks done". Thus, we can write them unconditionally without any effect. Note: The ACPI timer emulation can only be used by SoCs with microcode supporting CTC (Common Timer Copy) / ACPI timer emulation. Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/45951 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/common/block/include/intelblocks/cpulib.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/soc/intel/common/block/include') diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h index d2b00efb2f..4dfbef48f6 100644 --- a/src/soc/intel/common/block/include/intelblocks/cpulib.h +++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h @@ -156,4 +156,10 @@ void cpu_lt_lock_memory(void *unused); /* Get a supported PRMRR size in bytes with respect to users choice */ int get_valid_prmrr_size(void); +/* + * Enable the emulated ACPI timer in case it's not available or to allow + * disabling the PM ACPI timer (PM1_TMR) for power saving. + */ +void enable_pm_timer_emulation(void); + #endif /* SOC_INTEL_COMMON_BLOCK_CPULIB_H */ -- cgit v1.2.3