From 2153ea5b83461547c854b2cd784b1638a3feeb31 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 22 Nov 2017 15:38:19 +0530 Subject: soc/intel/common/block: Add Intel common PMC controller support for KBL, APL SoC needs to select specific macros to compile commom PMC code. TEST=Build and boot KBL (soraka/eve), APL (reef) Change-Id: Iacc8da986c01e9ac7516643dafc6d932ebe0ee5e Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/22563 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh --- .../intel/common/block/include/intelblocks/pmc.h | 67 ++++++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 src/soc/intel/common/block/include/intelblocks/pmc.h (limited to 'src/soc/intel/common/block/include') diff --git a/src/soc/intel/common/block/include/intelblocks/pmc.h b/src/soc/intel/common/block/include/intelblocks/pmc.h new file mode 100644 index 0000000000..850cda178b --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/pmc.h @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_COMMON_BLOCK_PMC_H +#define SOC_INTEL_COMMON_BLOCK_PMC_H + +#include +#include + +/* PMC controller resource structure */ +struct pmc_resource_config { + /* PMC PCI config offset for MMIO BAR */ + uint8_t pwrmbase_offset; + /* MMIO BAR address */ + uintptr_t pwrmbase_addr; + /* MMIO BAR size */ + size_t pwrmbase_size; + /* PMC PCI config offset for IO BAR */ + uint8_t abase_offset; + /* IO BAR address */ + uintptr_t abase_addr; + /* IO BAR size */ + size_t abase_size; +}; + +/* + * SoC overrides + * + * All new SoCs wishes to make use of common PMC PCI driver + * must implement below functionality . + */ + +/* + * Function to initialize PMC controller. + * + * This initialization may differ between different SoC + * + * Input: Device Structure PMC PCI device + */ +void pmc_soc_init(struct device *dev); + +/* + * SoC should fill this structure information based on + * PMC controller register information like PWRMBASE, ABASE offset + * BAR and Size + * + * Input: PMC config structure + * Output: -1 = Error, 0 = Success + */ +int pmc_soc_get_resources(struct pmc_resource_config *cfg); + +/* API to set ACPI mode */ +void pmc_set_acpi_mode(void); + +#endif /* SOC_INTEL_COMMON_BLOCK_PMC_H */ -- cgit v1.2.3