From d28bd0c79e47f425711eade50c9e2e5bb8cb2d86 Mon Sep 17 00:00:00 2001 From: Hannah Williams Date: Wed, 17 May 2017 23:24:22 -0700 Subject: soc/intel/common/block/gpio: Port gpio code from Apollolake to common Change-Id: Ic48401e92103ff0ec278fb69a3d304148a2d79aa Signed-off-by: Hannah Williams Reviewed-on: https://review.coreboot.org/19759 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- .../intel/common/block/include/intelblocks/gpio.h | 144 +++++++++ .../common/block/include/intelblocks/gpio_defs.h | 338 +++++++++++++++++++++ 2 files changed, 482 insertions(+) create mode 100644 src/soc/intel/common/block/include/intelblocks/gpio.h create mode 100644 src/soc/intel/common/block/include/intelblocks/gpio_defs.h (limited to 'src/soc/intel/common/block/include/intelblocks') diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h new file mode 100644 index 0000000000..c1542be6e7 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/gpio.h @@ -0,0 +1,144 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_INTELBLOCKS_GPIO_H_ +#define _SOC_INTELBLOCKS_GPIO_H_ + +#include +#include "gpio_defs.h" + +#ifndef __ACPI__ +#include + +/* + * Following should be defined in soc/gpio.h + * GPIO_MISCCFG - offset to GPIO MISCCFG Register + * + * GPIO_NUM_PAD_CFG_REGS - number of PAD config registers in the SOC + * For SOCs that have DW0 and DW1, it should be 2 + * NUM_GPI_STATUS_REGS - total number of GPI status registers across all + * GPIO communities in the SOC + * + * The register offsets specific to the soc communities should be provided in + * struct pad_community table returned from soc_gpio_get_community + */ + +typedef uint32_t gpio_t; + +struct pad_config { + int pad;/* offset of pad within community */ + uint32_t pad_config[GPIO_NUM_PAD_CFG_REGS];/* + Pad config data corresponding to DW0, DW1,.... */ +}; + +/* + * Structure provides the logical to actual value for PADRSTCFG in DW0 + */ +struct reset_mapping { + int logical;/* logical value defined in + include/intelblocks/gpio_defs.h - PAD_CFG0_RESET_xxx */ + int chipset;/* translation of logical to SOC PADRSTCFG */ +}; + +/* This structure will be used to describe a community or each group within a + * community when multiple groups exist inside a community + */ +struct pad_community { + const char *name; + const char *acpi_path; + size_t num_gpi_regs;/* number of gpi registers in community */ + size_t max_pads_per_group; /* number of pads in each group; + Number of pads bit mapped in each GPI status/en and Host Own Reg */ + gpio_t first_pad; /* first pad in community */ + gpio_t last_pad; /* last pad in community */ + uint16_t host_own_reg_0; /* offset to Host Ownership Reg 0 */ + uint16_t gpi_smi_sts_reg_0; /* offset to GPI SMI EN Reg 0 */ + uint16_t gpi_smi_en_reg_0; /* offset to GPI SMI STS Reg 0 */ + uint16_t pad_cfg_base; /* offset to first PAD_GFG_DW0 Reg */ + uint8_t gpi_status_offset; /* specifies offset in struct + gpi_status */ + uint8_t port; /* PCR Port ID */ + const struct reset_mapping *reset_map; /* PADRSTCFG logical to + chipset mapping */ + size_t num_reset_vals; +}; + +/* + * Provides storage for all GPI status registers from all communities + */ +struct gpi_status { + uint32_t grp[NUM_GPI_STATUS_REGS]; +}; + +/* + * Structure provides the pmc to gpio group mapping + */ +struct pmc_to_gpio_route { + int pmc; + int gpio; +}; + +/* + * Returns the first community in the list. This will help to iterate + * through the list. It also returns total number of gpio communities. + * The soc layer provides a table describing available gpio communities. + */ +const struct pad_community *soc_gpio_get_community(size_t *num_communities); + +/* + * Clear GPI SMI status and fill in the structure representing enabled + * and set status. + */ +void gpi_clear_get_smi_status(struct gpi_status *sts); + +/* Return 1 if gpio is set in the sts. Otherwise 0. */ +int gpi_status_get(const struct gpi_status *sts, gpio_t gpi); + +/* + * Configuration for raw pads. Some pads are designated as only special function + * pins, and don't have an associated GPIO number, so we need to expose the raw + * pad configuration functionality. + */ +void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads); + +/* + * Calculate Address of DW0 register for given GPIO + */ +void *gpio_dwx_address(const gpio_t pad); + +/* + * Returns the pmc_gpe to gpio_gpe mapping table + * + */ +const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num); + +/* + * Set the GPIO groups for the GPE blocks. The values from PMC register GPE_CFG + * are passed which is then mapped to proper groups for MISCCFG. This basically + * sets the MISCCFG register bits: + * dw0 = gpe0_route[11:8]. This is ACPI GPE0b. + * dw1 = gpe0_route[15:12]. This is ACPI GPE0c. + * dw2 = gpe0_route[19:16]. This is ACPI GPE0d. + */ +void gpio_route_gpe(uint8_t gpe0b, uint8_t gpe0c, uint8_t gpe0d); + +/* + * Function returns PCR port ID for this pad + */ +uint8_t gpio_get_pad_portid(const gpio_t pad); + +#endif +#endif /* _SOC_INTELBLOCKS_GPIO_H_ */ diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h new file mode 100644 index 0000000000..5085af462d --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -0,0 +1,338 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_BLOCK_GPIO_DEFS_H_ +#define _SOC_BLOCK_GPIO_DEFS_H_ + +#define PAD_CFG0_TX_STATE_BIT 0 +#define PAD_CFG0_TX_STATE (1 << PAD_CFG0_TX_STATE_BIT) +#define PAD_CFG0_RX_STATE_BIT 1 +#define PAD_CFG0_RX_STATE (1 << PAD_CFG0_RX_STATE_BIT) +#define PAD_CFG0_TX_DISABLE (1 << 8) +#define PAD_CFG0_RX_DISABLE (1 << 9) +#define PAD_CFG0_MODE_MASK (7 << 10) +#define PAD_CFG0_MODE_GPIO (0 << 10) +#define PAD_CFG0_MODE_FUNC(x) ((x) << 10) +#define PAD_CFG0_MODE_NF1 (1 << 10) +#define PAD_CFG0_MODE_NF2 (2 << 10) +#define PAD_CFG0_MODE_NF3 (3 << 10) +#define PAD_CFG0_MODE_NF4 (4 << 10) +#define PAD_CFG0_MODE_NF5 (5 << 10) +#define PAD_CFG0_MODE_NF6 (6 << 10) +#define PAD_CFG0_ROUTE_MASK (0xF << 17) +#define PAD_CFG0_ROUTE_NMI (1 << 17) +#define PAD_CFG0_ROUTE_SMI (1 << 18) +#define PAD_CFG0_ROUTE_SCI (1 << 19) +#define PAD_CFG0_ROUTE_IOAPIC (1 << 20) +#define PAD_CFG0_RXTENCFG_MASK (3 << 21) +#define PAD_CFG0_RXINV_MASK (1 << 23) +#define PAD_CFG0_RX_POL_INVERT (1 << 23) +#define PAD_CFG0_RX_POL_NONE (0 << 23) +#define PAD_CFG0_PREGFRXSEL (1 << 24) +#define PAD_CFG0_TRIG_MASK (3 << 25) +#define PAD_CFG0_TRIG_LEVEL (0 << 25) +#define PAD_CFG0_TRIG_EDGE_SINGLE (1 << 25) /* controlled by RX_INVERT*/ +#define PAD_CFG0_TRIG_OFF (2 << 25) +#define PAD_CFG0_TRIG_EDGE_BOTH (3 << 25) +#define PAD_CFG0_RXRAW1_MASK (1 << 28) +#define PAD_CFG0_RXPADSTSEL_MASK (1 << 29) +#define PAD_CFG0_RESET_MASK (3 << 30) +#define PAD_CFG0_RESET_PWROK (0 << 30) /* Logical PADRSTCFG value */ +#define PAD_CFG0_RESET_DEEP (1 << 30) /* Logical PADRSTCFG value */ +#define PAD_CFG0_RESET_PLTRST (2 << 30) /* Logical PADRSTCFG value */ +#define PAD_CFG0_RESET_RSMRST (3 << 30) /* Logical PADRSTCFG value */ +/* The PAD_CFG0_RESET_xxx are logical values and the actual chipset values + corresponding to these will be replaced by code in + soc/intel/common/block/gpio + */ + +/* Use the fourth bit in IntSel field to indicate gpio + * ownership. This field is RO and hence not used during + * gpio configuration. + */ +#define PAD_CFG1_GPIO_DRIVER (0x1 << 4) +#define PAD_CFG1_IRQ_MASK (0xff << 0) +#define PAD_CFG1_IOSTERM_MASK (0x3 << 8) +#define PAD_CFG1_IOSTERM_SAME (0x0 << 8) +#define PAD_CFG1_IOSTERM_DISPUPD (0x1 << 8) +#define PAD_CFG1_IOSTERM_ENPD (0x2 << 8) +#define PAD_CFG1_IOSTERM_ENPU (0x3 << 8) +#define PAD_CFG1_PULL_MASK (0xf << 10) +#define PAD_CFG1_PULL_NONE (0x0 << 10) +#define PAD_CFG1_PULL_DN_5K (0x2 << 10) +#define PAD_CFG1_PULL_DN_20K (0x4 << 10) +#define PAD_CFG1_PULL_UP_1K (0x9 << 10) +#define PAD_CFG1_PULL_UP_5K (0xa << 10) +#define PAD_CFG1_PULL_UP_2K (0xb << 10) +#define PAD_CFG1_PULL_UP_20K (0xc << 10) +#define PAD_CFG1_PULL_UP_667 (0xd << 10) +#define PAD_CFG1_PULL_NATIVE (0xf << 10) +#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY) +/* Tx enabled driving last value driven, Rx enabled */ +#define PAD_CFG1_IOSSTATE_TxLASTRxE (0x0 << 14) +/* Tx enabled driving 0, Rx disabled and Rx driving 0 back to its controller + * internally */ +#define PAD_CFG1_IOSSTATE_Tx0RxDCRx0 (0x1 << 14) +/* Tx enabled driving 0, Rx disabled and Rx driving 1 back to its controller + * internally */ +#define PAD_CFG1_IOSSTATE_Tx0RXDCRx1 (0x2 << 14) +/* Tx enabled driving 1, Rx disabled and Rx driving 0 back to its controller + * internally */ +#define PAD_CFG1_IOSSTATE_Tx1RXDCRx0 (0x3 << 14) +/* Tx enabled driving 1, Rx disabled and Rx driving 1 back to its controller + * internally */ +#define PAD_CFG1_IOSSTATE_Tx1RxDCRx1 (0x4 << 14) +/* Tx enabled driving 0, Rx enabled */ +#define PAD_CFG1_IOSSTATE_Tx0RxE (0x5 << 14) +/* Tx enabled driving 1, Rx enabled */ +#define PAD_CFG1_IOSSTATE_Tx1RxE (0x6 << 14) +/* Hi-Z, Rx driving 0 back to its controller internally */ +#define PAD_CFG1_IOSSTATE_HIZCRx0 (0x7 << 14) +/* Hi-Z, Rx driving 1 back to its controller internally */ +#define PAD_CFG1_IOSSTATE_HIZCRx1 (0x8 << 14) +#define PAD_CFG1_IOSSTATE_TxDRxE (0x9 << 14) /* Tx disabled, Rx enabled */ +#define PAD_CFG1_IOSSTATE_IGNORE (0xf << 14) /* Ignore Iostandby */ +#define PAD_CFG1_IOSSTATE_MASK (0xf << 14) /* mask to extract Iostandby bits */ +#define PAD_CFG1_IOSSTATE_SHIFT 14 /* set Iostandby bits [17:14] */ +#else /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY */ +#define PAD_CFG1_IOSSTATE_MASK 0 +#endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY */ + +/* voltage tolerance 0=3.3V default 1=1.8V tolerant */ +#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL) +#define PAD_CFG1_TOL_MASK (0x1 << 25) +#define PAD_CFG1_TOL_1V8 (0x1 << 25) +#endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL */ + +#define PAD_FUNC(value) PAD_CFG0_MODE_##value +#define PAD_RESET(value) PAD_CFG0_RESET_##value +#define PAD_PULL(value) PAD_CFG1_PULL_##value + +#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY) +#define PAD_IOSSTATE(value) PAD_CFG1_IOSSTATE_##value +#define PAD_IOSTERM(value) PAD_CFG1_IOSTERM_##value +#else +#define PAD_IOSSTATE(value) 0 +#define PAD_IOSTERM(value) 0 +#endif + +#define PAD_IRQ_CFG(route, trig, inv) \ + (PAD_CFG0_ROUTE_##route | \ + PAD_CFG0_TRIG_##trig | \ + PAD_CFG0_RX_POL_##inv) + +#define _PAD_CFG_STRUCT(__pad, __config0, __config1) \ + { \ + .pad = __pad, \ + .pad_config[0] = __config0, \ + .pad_config[1] = __config1, \ + } + +/* Native function configuration */ +#define PAD_CFG_NF(pad, pull, rst, func) \ + _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ + PAD_IOSSTATE(TxLASTRxE)) + +#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL) +/* Native 1.8V tolerant pad, only applies to some pads like I2C/I2S + Not applicable to all SOCs. Refer EDS + */ +#define PAD_CFG_NF_1V8(pad, pull, rst, func) \ + _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) |\ + PAD_IOSSTATE(TxLASTRxE) | PAD_CFG1_TOL_1V8) +#endif + +/* Native function configuration for standby state */ +#define PAD_CFG_NF_IOSSTATE(pad, pull, rst, func, iosstate) \ + _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ + PAD_IOSSTATE(iosstate)) + +/* Native function configuration for standby state, also configuring + iostandby as masked */ +#define PAD_CFG_NF_IOSTANDBY_IGNORE(pad, pull, rst, func) \ + _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ + PAD_IOSSTATE(IGNORE)) + +/* Native function configuration for standby state, also configuring + iosstate and iosterm */ +#define PAD_CFG_NF_IOSSTATE_IOSTERM(pad, pull, rst, func, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ + PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + +/* General purpose output, no pullup/down. */ +#define PAD_CFG_GPO(pad, val, rst) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ + PAD_PULL(NONE) | PAD_IOSSTATE(TxLASTRxE)) + +/* General purpose output, with termination specified */ +#define PAD_CFG_TERM_GPO(pad, val, pull, rst) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ + PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE)) + +/* General purpose output, no pullup/down. */ +#define PAD_CFG_GPO_GPIO_DRIVER(pad, val, rst, pull) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ + PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE) | PAD_CFG1_GPIO_DRIVER) + +/* General purpose output. */ +#define PAD_CFG_GPO_IOSSTATE_IOSTERM(pad, val, rst, pull, iosstate, ioterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ + PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(ioterm)) + +/* General purpose input */ +#define PAD_CFG_GPI(pad, pull, rst) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ + PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE)) + +/* General purpose input. The following macro sets the + * Host Software Pad Ownership to GPIO Driver mode. + */ +#define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ + PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TxLASTRxE)) + +#define PAD_CFG_GPIO_DRIVER_HI_Z(pad, pull, rst, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_CFG0_RX_DISABLE, \ + PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | \ + PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + +#define PAD_CFG_GPIO_HI_Z(pad, pull, rst, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_CFG0_RX_DISABLE, PAD_PULL(pull) | \ + PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + +/* GPIO Interrupt */ +#define PAD_CFG_GPI_INT(pad, pull, rst, trig) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_CFG0_TRIG_##trig | PAD_CFG0_RX_POL_NONE, \ + PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TxLASTRxE)) + +/* No Connect configuration for unused pad. + * NC should be GPI with Term as PU20K, PD20K, NONE depending upon default Term + */ +#define PAD_NC(pad, pull) PAD_CFG_GPI(pad, pull, DEEP) + +#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS) + +#define PAD_CFG_GPI_APIC(pad, pull, rst) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_IRQ_CFG(IOAPIC, LEVEL, NONE), PAD_PULL(pull)) + +#define PAD_CFG_GPI_APIC_INVERT(pad, pull, rst) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_IRQ_CFG(IOAPIC, LEVEL, INVERT), PAD_PULL(pull)) + +#define PAD_CFG_GPI_ACPI_SCI(pad, pull, rst, inv) \ + PAD_CFG_GPI_SCI(pad, pull, rst, EDGE_SINGLE, inv) + +#define PAD_CFG_GPI_ACPI_SMI(pad, pull, rst, inv) \ + PAD_CFG_GPI_SMI(pad, pull, rst, EDGE_SINGLE, inv) + +#define PAD_CFG_NC(pad) PAD_NC(pad, NONE) + +#define PAD_CFG1_PULL_20K_PU PAD_CFG1_PULL_UP_20K +#define PAD_CFG1_PULL_5K_PU PAD_CFG1_PULL_UP_5K +#define PAD_CFG1_PULL_20K_PD PAD_CFG1_PULL_DN_20K +#define PAD_CFG0_TRIG_EDGE PAD_CFG0_TRIG_EDGE_SINGLE +#define PAD_CFG0_RX_POL_YES PAD_CFG0_RX_POL_INVERT + +#else +/* General purpose input, routed to APIC */ +#define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ + PAD_IOSSTATE(TxLASTRxE)) +#endif + +/* General purpose input, routed to APIC - with IOStandby Config*/ +#define PAD_CFG_GPI_APIC_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ + PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + +/* + * The following APIC macros assume the APIC will handle the filtering + * on its own end. One just needs to pass an active high message into the + * ITSS. + */ +#define PAD_CFG_GPI_APIC_LOW(pad, pull, rst) \ + PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, INVERT) + +#define PAD_CFG_GPI_APIC_HIGH(pad, pull, rst) \ + PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, NONE) + +/* General purpose input, routed to SMI */ +#define PAD_CFG_GPI_SMI(pad, pull, rst, trig, inv) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \ + PAD_IOSSTATE(TxLASTRxE)) + +/* General purpose input, routed to SMI */ +#define PAD_CFG_GPI_SMI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \ + PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + +#define PAD_CFG_GPI_SMI_LOW(pad, pull, rst, trig) \ + PAD_CFG_GPI_SMI(pad, pull, rst, trig, INVERT) + +#define PAD_CFG_GPI_SMI_HIGH(pad, pull, rst, trig) \ + PAD_CFG_GPI_SMI(pad, pull, rst, trig, NONE) + +/* General purpose input, routed to SCI */ +#define PAD_CFG_GPI_SCI(pad, pull, rst, trig, inv) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ + PAD_IOSSTATE(TxLASTRxE)) + +/* General purpose input, routed to SCI */ +#define PAD_CFG_GPI_SCI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ + PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + +#define PAD_CFG_GPI_SCI_LOW(pad, pull, rst, trig) \ + PAD_CFG_GPI_SCI(pad, pull, rst, trig, INVERT) + +#define PAD_CFG_GPI_SCI_HIGH(pad, pull, rst, trig) \ + PAD_CFG_GPI_SCI(pad, pull, rst, trig, NONE) + +/* General purpose input, routed to NMI */ +#define PAD_CFG_GPI_NMI(pad, pull, rst, trig, inv) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_IRQ_CFG(NMI, trig, inv), PAD_PULL(pull) | \ + PAD_IOSSTATE(TxLASTRxE)) + +#endif /* _SOC_BLOCK_GPIO_DEFS_H_ */ -- cgit v1.2.3