From 8971ccd576a7b0edbd02101b0c3bc3541cb6a741 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 29 Sep 2020 14:36:40 +0530 Subject: soc/intel: Move pch_misc_init() to common code List of changes: 1. Move pch_misc_init() into common block code. 2. Remove redundant LPC functions from SoC directory and refer from block/lpc directory. 3. Create macros for IO port 0x61 and 0x70 as applicable. TEST=Able to build and boot hatch and tglrvp platform without seeing any functional impact. Change-Id: Ie36ee63869c076d251ccfa5409001d18f22600d7 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/45789 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Angel Pons --- src/soc/intel/common/block/include/intelblocks/lpc_lib.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/soc/intel/common/block/include/intelblocks') diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h index 52b0ff8e72..b04df76844 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h +++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h @@ -109,5 +109,11 @@ void pch_lpc_add_new_resource(struct device *dev, uint8_t offset, void pch_enable_ioapic(void); /* Retrieve and setup PCH LPC interrupt routing. */ void pch_pirq_init(void); +/* + * LPC MISC programming + * 1. Setup NMI on errors, disable SERR + * 2. Disable NMI sources + */ +void pch_misc_init(void); #endif /* _SOC_COMMON_BLOCK_LPC_LIB_H_ */ -- cgit v1.2.3