From 7609c654b18b232bd0b45621ebd3921d14db8a39 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 19 May 2017 14:50:09 +0530 Subject: soc/intel/common/block: Add Intel common systemagent support Add Intel common systemagent support for romstage and ramstage. Include soc specific macros need to compile systemagent common code. Change-Id: I969ff187e3d4199864cb2e9c9a13f4d04158e27c Signed-off-by: V Sowmya Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/19668 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- .../common/block/include/intelblocks/systemagent.h | 81 ++++++++++++++++++---- 1 file changed, 68 insertions(+), 13 deletions(-) (limited to 'src/soc/intel/common/block/include/intelblocks') diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h index 77248bbb1a..22a2b8d043 100644 --- a/src/soc/intel/common/block/include/intelblocks/systemagent.h +++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h @@ -16,22 +16,77 @@ #ifndef SOC_INTEL_COMMON_BLOCK_SA_H #define SOC_INTEL_COMMON_BLOCK_SA_H -/* Device 0:0.0 PCI configuration space */ +#include +#include +#include -#define MCHBAR 0x48 -#define PCIEXBAR 0x60 -#define PCIEXBAR_LENGTH_64MB 2 -#define PCIEXBAR_LENGTH_128MB 1 -#define PCIEXBAR_LENGTH_256MB 0 -#define PCIEXBAR_PCIEXBAREN (1 << 0) -#define GGC 0x50 +/* Device 0:0.0 PCI configuration space */ +#define MCHBAR 0x48 +#define PCIEXBAR 0x60 +#define TOUUD 0xa8 /* Top of Upper Usable DRAM */ +#define BDSM 0xb0 /* Base Data Stolen Memory */ +#define BGSM 0xb4 /* Base GTT Stolen Memory */ +#define TSEG 0xb8 /* TSEG base */ +#define TOLUD 0xbc /* Top of Low Used Memory */ -#define TOUUD 0xa8 /* Top of Upper Usable DRAM */ -#define BDSM 0xb0 /* Base Data Stolen Memory */ -#define BGSM 0xb4 /* Base GTT Stolen Memory */ -#define TSEG 0xb8 /* TSEG base */ -#define TOLUD 0xbc /* Top of Low Used Memory */ +/* MCHBAR */ +#define MCHBAR8(x) (*(volatile u8 *)(MCH_BASE_ADDRESS + x)) +#define MCHBAR16(x) (*(volatile u16 *)(MCH_BASE_ADDRESS + x)) +#define MCHBAR32(x) (*(volatile u32 *)(MCH_BASE_ADDRESS + x)) +/* Perform System Agent Initialization during Bootblock phase */ void bootblock_systemagent_early_init(void); +/* + * Fixed MMIO range + * INDEX = Either PCI configuration space registers or MMIO offsets + * mapped from REG. + * BASE = 32 bit Address. + * SIZE = base length + * DESCRIPTION = Name of the register/offset. + */ +struct sa_mmio_descriptor { + unsigned int index; + uintptr_t base; + size_t size; + const char *description; +}; + +/* API to set Fixed MMIO addresss into PCI configuration space */ +void sa_set_pci_bar(const struct sa_mmio_descriptor *fixed_set_resources, + size_t count); +/* API to set Fixed MMIO addresss into MCH base address */ +void sa_set_mch_bar(const struct sa_mmio_descriptor *fixed_set_resources, + size_t count); +/* + * API to program fixed mmio resource range based on SoC input + * struct sa_mmio_descriptor + */ +void sa_add_fixed_mmio_resources(struct device *dev, int *resource_cnt, + const struct sa_mmio_descriptor *sa_fixed_resources, size_t count); +/* + * API to set BIOS Reset CPL through MCHBAR + * SoC to provide BIOS_RESET_CPL register offset through soc/systemagent.h + */ +void enable_bios_reset_cpl(void); +/* API to enable PAM regisers */ +void enable_pam_region(void); +/* API to enable Power Aware Interrupt Routing through MCHBAR */ +void enable_power_aware_intr(void); + +/* + * SoC overrides + * + * All new SoC must implement below functionality for ramstage. + */ + +/* Perform System Agent Initialization during Ramstage phase */ +void soc_systemagent_init(struct device *dev); +/* + * SoC call to provide all known fixed memory ranges for Device 0:0.0. + * SoC function should provide fixed resource ranges in form of + * struct sa_mmio_descriptor along with resource count. + */ +void soc_add_fixed_mmio_resources(struct device *dev, int *resource_cnt); + #endif /* SOC_INTEL_COMMON_BLOCK_SA_H */ -- cgit v1.2.3