From 550fa21776b757207df025cee8f1ffaf9c680793 Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Fri, 1 Jun 2018 11:06:49 +0530 Subject: soc/intel/common: Add edge trigger configuartion for IOAPIC IRQ mode Change-Id: I4e1f009489f2d8338ae94b78d7e9eb3f88a85daa Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/26730 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh Reviewed-by: Subrata Banik --- src/soc/intel/common/block/include/intelblocks/gpio_defs.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/soc/intel/common/block/include/intelblocks') diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 244c680158..a8d5ac9eeb 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -284,6 +284,9 @@ #define PAD_CFG_GPI_APIC_HIGH(pad, pull, rst) \ PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, NONE) +#define PAD_CFG_GPI_APIC_EDGE_LOW(pad, pull, rst) \ + PAD_CFG_GPI_APIC(pad, pull, rst, EDGE_SINGLE, INVERT) + /* General purpose input, routed to SMI */ #define PAD_CFG_GPI_SMI(pad, pull, rst, trig, inv) \ _PAD_CFG_STRUCT(pad, \ -- cgit v1.2.3