From 3d32f915a9c4d60046574690db966d1f14eebe65 Mon Sep 17 00:00:00 2001 From: Gang Chen Date: Tue, 18 Jun 2024 06:39:12 +0800 Subject: soc/intel/xeon_sp: Reserve PRMRR PRMRR (Protected Region Memory Range Region) are not accessible as normal DRAM regions and needs to be explicitly reserved in memory map. Change-Id: I81d17b1376459510f7c0d43ba4b519b1f2bd3e1f Signed-off-by: Gang Chen Signed-off-by: Shuo Liu Signed-off-by: Jincheng Li Reviewed-on: https://review.coreboot.org/c/coreboot/+/84314 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/common/block/include/intelblocks/msr.h | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/common/block/include/intelblocks') diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index a03032899d..4bdd90c536 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -55,6 +55,7 @@ #define PWR_PERF_PLATFORM_OVR (1 << 18) #define VR_THERM_ALERT_DISABLE_LOCK (1 << 23) #define MSR_PRMRR_BASE_0 0x2a0 +#define MSR_PRMRR_BASE(reg) (MSR_PRMRR_BASE_0 + (reg)) #define MSR_EVICT_CTL 0x2e0 #define MSR_LT_CONTROL 0x2e7 #define LT_CONTROL_LOCK (1 << 0) -- cgit v1.2.3