From 2cc66916e5d5d5b0d2e92e180bae7ac64d30cbac Mon Sep 17 00:00:00 2001 From: Sridhar Siricilla Date: Sat, 31 Aug 2019 11:20:34 +0530 Subject: soc/intel/common/block/cse: Move me_read_config32() to common code me_read_config32() is defined in multiple places, move it to common location. Also, this function is usually used for reading HFSTS registers, hence move the HFSTS register definitions to common location. Also add a funtion to check if the CSE device has been enabled in the devicetree and it is visible on the bus. This API can be used by the caller to check before initiating any HECI communication. TEST=Verified reading HFSTS registers on CML RVP & Hatch board Change-Id: Icdbfb6b30a007d469b5e018a313c14586addb130 Signed-off-by: Sridhar Siricilla Signed-off-by: Rizwan Qureshi Reviewed-on: https://review.coreboot.org/c/coreboot/+/35225 Reviewed-by: Subrata Banik Reviewed-by: Aamir Bohra Reviewed-by: V Sowmya Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/include/intelblocks/cse.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'src/soc/intel/common/block/include/intelblocks') diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 424d483cfa..bce615c172 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -19,6 +19,16 @@ #include +/* HFSTS register offsets in PCI config space */ +enum { + PCI_ME_HFSTS1 = 0x40, + PCI_ME_HFSTS2 = 0x48, + PCI_ME_HFSTS3 = 0x60, + PCI_ME_HFSTS4 = 0x64, + PCI_ME_HFSTS5 = 0x68, + PCI_ME_HFSTS6 = 0x6C, +}; + /* set up device for use in early boot enviroument with temp bar */ void heci_init(uintptr_t bar); /* @@ -52,6 +62,16 @@ int heci_send_receive(const void *snd_msg, size_t snd_sz, void *rcv_msg, size_t */ int heci_reset(void); +/* Reads config value from a specified offset in the CSE PCI Config space. */ +uint32_t me_read_config32(int offset); + +/* + * Check if the CSE device is enabled in device tree. Also check if the device + * is visible on the PCI bus by reading config space. + * Return true if device present and config space enabled, else return false. + */ +bool is_cse_enabled(void); + #define BIOS_HOST_ADDR 0x00 #define HECI_MKHI_ADDR 0x07 -- cgit v1.2.3