From ae18f80febc3ecaacc0314e942a4f8b248bfcc4c Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Tue, 17 Apr 2018 11:37:28 -0600 Subject: cpu/x86: move NXE and PAT accesses to paging module The EFER and PAT MSRs are x86 architecturally defined. Therefore, move the macro defintions to msr.h. Add 'paging' prefix to the PAT and NXE pae/paging functions to namespace things a little better. BUG=b:72728953 Change-Id: I1ab2c4ff827e19d5ba4e3b6eaedb3fee6aaef14d Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/25713 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Justin TerAvest --- src/soc/intel/common/block/include/intelblocks/msr.h | 10 ---------- 1 file changed, 10 deletions(-) (limited to 'src/soc/intel/common/block/include/intelblocks/msr.h') diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index 5cfce17894..22e8862e98 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -72,7 +72,6 @@ #define PRMRR_PHYS_MASK_LOCK (1 << 10) #define PRMRR_PHYS_MASK_VALID (1 << 11) #define MSR_POWER_CTL 0x1fc -#define MSR_IA32_PAT 0x277 #define MSR_EVICT_CTL 0x2e0 #define MSR_SGX_OWNEREPOCH0 0x300 #define MSR_SGX_OWNEREPOCH1 0x301 @@ -143,13 +142,4 @@ #define SGX_RESOURCE_MASK_LO (0xfffff000UL) #define SGX_RESOURCE_MASK_HI (0xfffffUL) -/* Intel SDM: Table 2-1 - * IA-32 architectural MSR: Extended Feature Enable Register - */ -#define IA32_EFER 0xC0000080 -#define EFER_NXE (1 << 11) -#define EFER_LMA (1 << 10) -#define EFER_LME (1 << 8) -#define EFER_SCE (1 << 0) - #endif /* SOC_INTEL_COMMON_MSR_H */ -- cgit v1.2.3