From 50db9a208e743ecbbadfde6643e7aeaf425eacdf Mon Sep 17 00:00:00 2001 From: Shelley Chen Date: Wed, 31 Jan 2018 15:55:50 -0800 Subject: soc/intel/skylake: Set PsysPl3 and Pl4 If given a value for PsysPl3 and/or Pl4, set the appropriate MSR. BUG=b:71594855 BRANCH=None TEST=boot up and check MSRs in OS to make sure values are set as expected. Test on Fizz, which will set these values in mainboard. Change-Id: Idbe04f48079b4fa3302d21acd065f2e4c53dd1ed Signed-off-by: Shelley Chen Reviewed-on: https://review.coreboot.org/23527 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Gaggery Tsai --- src/soc/intel/common/block/include/intelblocks/msr.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/soc/intel/common/block/include/intelblocks/msr.h') diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index 45f201c7da..7aa81f09ea 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -114,6 +114,8 @@ #define PKG_POWER_LIMIT_CLAMP (1 << 16) #define PKG_POWER_LIMIT_TIME_SHIFT 17 #define PKG_POWER_LIMIT_TIME_MASK (0x7f) +#define PKG_POWER_LIMIT_DUTYCYCLE_SHIFT 24 +#define PKG_POWER_LIMIT_DUTYCYCLE_MASK (0x7f) /* SMM save state MSRs */ #define SMBASE_MSR 0xc20 #define IEDBASE_MSR 0xc22 -- cgit v1.2.3