From 2b69b21c2db20ddce1f04e72b3eaa1d624540845 Mon Sep 17 00:00:00 2001 From: Cole Nelson Date: Tue, 12 Jun 2018 09:56:24 -0700 Subject: soc/intel/common: defines constant for C1E enable mask Register 0x1fc (MSR_POWER_CTL) deserves a proper mask for the C1E enable bit. Define POWER_CTL_C1E_MASK to be used subsequently. Change-Id: I7a5408f6678f56540929b7811764845b6dad1149 Signed-off-by: Cole Nelson Reviewed-on: https://review.coreboot.org/27035 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/include/intelblocks/msr.h | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/common/block/include/intelblocks/msr.h') diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index 22e8862e98..e1fc431f3a 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -72,6 +72,7 @@ #define PRMRR_PHYS_MASK_LOCK (1 << 10) #define PRMRR_PHYS_MASK_VALID (1 << 11) #define MSR_POWER_CTL 0x1fc +#define POWER_CTL_C1E_MASK (1 << 1) #define MSR_EVICT_CTL 0x2e0 #define MSR_SGX_OWNEREPOCH0 0x300 #define MSR_SGX_OWNEREPOCH1 0x301 -- cgit v1.2.3