From 89331cd4c877397adf6b35002d864ac105dfc827 Mon Sep 17 00:00:00 2001 From: Barnali Sarkar Date: Thu, 16 Feb 2017 17:22:37 +0530 Subject: soc/intel/common/block: Add Intel common FAST_SPI code Create Intel Common FAST_SPI Controller code. This code contains the code for SPI initialization which has the following programming - * Get BIOS Rom Region Size * Enable SPIBAR * Disable the BIOS write protect so write commands are allowed * Enable SPI Prefetching and Caching. * SPI Controller register offsets in the common header fast_spi.h * Implement FAST_SPI read, write, erase APIs. Change-Id: I046e3b30c8efb172851dd17f49565c9ec4cb38cb Signed-off-by: Barnali Sarkar Reviewed-on: https://review.coreboot.org/18557 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh --- .../common/block/include/intelblocks/fast_spi.h | 67 ++++++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 src/soc/intel/common/block/include/intelblocks/fast_spi.h (limited to 'src/soc/intel/common/block/include/intelblocks/fast_spi.h') diff --git a/src/soc/intel/common/block/include/intelblocks/fast_spi.h b/src/soc/intel/common/block/include/intelblocks/fast_spi.h new file mode 100644 index 0000000000..2b80c49837 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/fast_spi.h @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_COMMON_BLOCK_FAST_SPI_H +#define SOC_INTEL_COMMON_BLOCK_FAST_SPI_H + +#include +#include + +/* + * Disable the BIOS write protect and Enable Prefetching and Caching. + */ +void fast_spi_init(void); +/* + * Minimal set of commands to read WPSR from SPI. + * Returns 0 on success, < 0 on failure. + */ +int fast_spi_flash_read_wpsr(u8 *sr); +/* + * Set FAST_SPIBAR BIOS Control BILD bit. + */ +void fast_spi_set_bios_interface_lock_down(void); +/* + * Set FAST_SPIBAR BIOS Control LE bit. + */ +void fast_spi_set_lock_enable(void); +/* + * Set FAST_SPIBAR BIOS Control EISS bit. + */ +void fast_spi_set_eiss(void); +/* + * Set FAST_SPI opcode menu. + */ +void fast_spi_set_opcode_menu(void); +/* + * Lock FAST_SPIBAR. + */ +void fast_spi_lock_bar(void); +/* + * Set FAST_SPIBAR Soft Reset Data Register value. + */ +void fast_spi_set_strap_msg_data(uint32_t soft_reset_data); +/* + * Returns bios_start and fills in size of the BIOS region. + */ +size_t fast_spi_get_bios_region(size_t *bios_size); +/* + * Program temporary BAR for FAST_SPI in case any of the stages before ramstage + * need to access FAST_SPI MMIO regs. Ramstage will assign a new BAR during PCI + * enumeration. Also, Disable the BIOS write protect and Enable Prefetching and + * Caching. + */ +void fast_spi_early_init(uintptr_t spi_base_address); + +#endif /* SOC_INTEL_COMMON_BLOCK_FAST_SPI_H */ -- cgit v1.2.3