From 32d47eb688390d08e0f3f839df69371b55af8889 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Sat, 28 Sep 2019 00:00:30 +0300 Subject: soc/intel: Rename MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The filename chip.h has a special purpose with the generation of static devicetree, where the configuration structure name matches the path to the chip.h file. For example, soc/intel/skylake/chip.h defines struct soc_intel_skylake_config. The renamed file did not follow this convention and the structure it defines would conflict with one defined soc/intel/common/chip.h if such is ever added. Change-Id: Id3d56bf092c6111d2293136865b053b095e92d6b Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35657 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh --- .../intel/common/block/include/intelblocks/cfg.h | 45 ++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 src/soc/intel/common/block/include/intelblocks/cfg.h (limited to 'src/soc/intel/common/block/include/intelblocks/cfg.h') diff --git a/src/soc/intel/common/block/include/intelblocks/cfg.h b/src/soc/intel/common/block/include/intelblocks/cfg.h new file mode 100644 index 0000000000..e7e381bfe4 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/cfg.h @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_COMMON_BLOCK_CFG_H +#define SOC_INTEL_COMMON_BLOCK_CFG_H + +#include +#include +#include + +enum { + CHIPSET_LOCKDOWN_FSP = 0, /* FSP handles locking per UPDs */ + CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */ +}; + +/* + * This structure will hold data required by common blocks. + * These are soc specific configurations which will be filled by soc. + * We'll fill this structure once during init and use the data in common block. + */ +struct soc_intel_common_config { + int chipset_lockdown; + struct gspi_cfg gspi[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + struct dw_i2c_bus_config i2c[CONFIG_SOC_INTEL_I2C_DEV_MAX]; + /* PCH Thermal Trip Temperature in deg C */ + uint8_t pch_thermal_trip; + struct mmc_dll_params emmc_dll; +}; + +/* This function to retrieve soc config structure required by common code */ +const struct soc_intel_common_config *chip_get_common_soc_structure(void); + +#endif /* SOC_INTEL_COMMON_BLOCK_CFG_H */ -- cgit v1.2.3