From 108f87262bf47ce3549fa0c5ed16a40fe916656f Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 31 Mar 2017 17:10:02 -0700 Subject: soc/intel/common: Add support for common GSPI controller Add support for GSPI controller in Intel PCH. This controller is compliant with PXA2xx SPI controller with some additional registers to provide more fine-grained control of the SPI bus. Currently, DMA is not enabled as this driver might be used before memory is up (e.g. TPM on SPI). Also, provide common GSPI config structure that can be included by SoCs in chip config to allow mainboards to configure GSPI bus. Additionally, provide an option for SoCs to configure BAR for GSPI controllers before memory is up. BUG=b:35583330 Change-Id: I0eb91eba2c523be457fee8922c44fb500a9fa140 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/19098 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/common/block/gspi/Makefile.inc | 4 ++++ 1 file changed, 4 insertions(+) create mode 100644 src/soc/intel/common/block/gspi/Makefile.inc (limited to 'src/soc/intel/common/block/gspi/Makefile.inc') diff --git a/src/soc/intel/common/block/gspi/Makefile.inc b/src/soc/intel/common/block/gspi/Makefile.inc new file mode 100644 index 0000000000..85cb18ebb8 --- /dev/null +++ b/src/soc/intel/common/block/gspi/Makefile.inc @@ -0,0 +1,4 @@ +bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI) += gspi.c +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI) += gspi.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI) += gspi.c +verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI) += gspi.c -- cgit v1.2.3