From d28bd0c79e47f425711eade50c9e2e5bb8cb2d86 Mon Sep 17 00:00:00 2001 From: Hannah Williams Date: Wed, 17 May 2017 23:24:22 -0700 Subject: soc/intel/common/block/gpio: Port gpio code from Apollolake to common Change-Id: Ic48401e92103ff0ec278fb69a3d304148a2d79aa Signed-off-by: Hannah Williams Reviewed-on: https://review.coreboot.org/19759 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/common/block/gpio/Kconfig | 36 +++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 src/soc/intel/common/block/gpio/Kconfig (limited to 'src/soc/intel/common/block/gpio/Kconfig') diff --git a/src/soc/intel/common/block/gpio/Kconfig b/src/soc/intel/common/block/gpio/Kconfig new file mode 100644 index 0000000000..bd2651f637 --- /dev/null +++ b/src/soc/intel/common/block/gpio/Kconfig @@ -0,0 +1,36 @@ +config SOC_INTEL_COMMON_BLOCK_GPIO + bool + help + Intel Processor common GPIO support + +config DEBUG_SOC_COMMON_BLOCK_GPIO + depends on SOC_INTEL_COMMON_BLOCK_GPIO + bool "Output verbose GPIO debug messages" + default n + help + This option enables GPIO debug messages + +# Used in small core SOCs to invert the polarity as ITSS only takes +# active high signals +config SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG + depends on SOC_INTEL_COMMON_BLOCK_GPIO + bool + default n + +# Used to configure Pad Tolerance as 1.8V or 3.3V +config SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL + depends on SOC_INTEL_COMMON_BLOCK_GPIO + bool + default n + +# Used to configure IOSSTATE and IOSTERM +config SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY + depends on SOC_INTEL_COMMON_BLOCK_GPIO + bool + default n + +# Used to provide support for legacy macros +config SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS + depends on SOC_INTEL_COMMON_BLOCK_GPIO + bool + default n -- cgit v1.2.3