From def18c4068cf1d07cc67f71d62e0ac5bc7e84afa Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 31 Mar 2022 00:16:00 +0530 Subject: soc/intel/common/block/fast_spi: Refactor ROM caching implementation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch removes different implementation to cache the SPI ROM between early and later boot stage where SPI ROM caching doesn't need even advanced implementation like `mtrr_use_temp_range()` as SPI ROM ranage is always mapped to below 4GB hence, simple `set_var_mtrr()` function can be sufficient without any additional complexity. BUG=b:225766934 TEST=Calling into `fast_spi_cache_bios_region()` from ramstage is able to update the temporary variable range MTRRs and showed ~44ms of boot time savings as below: Before: 90:starting to load payload             1,084,052 (14)   15:starting LZMA decompress (ignore for x86)   1,084,121 (68)   16:finished LZMA decompress (ignore for x86)   1,140,742 (56,620) After: 90:starting to load payload              1,090,433 (14)   15:starting LZMA decompress (ignore for x86)   1,090,650 (217)   16:finished LZMA decompress (ignore for x86)   1,102,896 (12,245) Signed-off-by: Subrata Banik Change-Id: I43973b45dc6d032cfcc920eeb36b37fe027e6e8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63221 Reviewed-by: Tim Wawrzynczak Reviewed-by: Arthur Heymans Reviewed-by: Nick Vaccaro Reviewed-by: Eric Lai Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/fast_spi/fast_spi.c | 35 +++++++++++--------------- 1 file changed, 15 insertions(+), 20 deletions(-) (limited to 'src/soc/intel/common/block/fast_spi') diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 7be71a26fb..5a76df3d37 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -196,6 +197,18 @@ void fast_spi_set_strap_msg_data(uint32_t soft_reset_data) write32(spibar + SPIBAR_RESET_LOCK, ssl); } +static void fast_spi_enable_cache_range(unsigned int base, unsigned int size) +{ + const int type = MTRR_TYPE_WRPROT; + int mtrr = get_free_var_mtrr(); + if (mtrr == -1) { + printk(BIOS_WARNING, "ROM caching failed due to no free MTRR available!\n"); + return; + } + + set_var_mtrr(mtrr, base, size, type); +} + /* * Returns bios_start and fills in size of the BIOS region. */ @@ -240,19 +253,11 @@ static void fast_spi_cache_ext_bios_window(void) { size_t ext_bios_size; uintptr_t ext_bios_base; - const int type = MTRR_TYPE_WRPROT; if (!fast_spi_ext_bios_cache_range(&ext_bios_base, &ext_bios_size)) return; - if (ENV_PAYLOAD_LOADER) { - mtrr_use_temp_range(ext_bios_base, ext_bios_size, type); - } else { - int mtrr = get_free_var_mtrr(); - if (mtrr == -1) - return; - set_var_mtrr(mtrr, ext_bios_base, ext_bios_size, type); - } + fast_spi_enable_cache_range(ext_bios_base, ext_bios_size); } void fast_spi_cache_ext_bios_postcar(struct postcar_frame *pcf) @@ -271,7 +276,6 @@ void fast_spi_cache_bios_region(void) { size_t bios_size; uint32_t alignment; - const int type = MTRR_TYPE_WRPROT; uintptr_t base; /* Only the IFD BIOS region is memory mapped (at top of 4G) */ @@ -290,16 +294,7 @@ void fast_spi_cache_bios_region(void) bios_size = ALIGN_UP(bios_size, alignment); base = 4ULL*GiB - bios_size; - if (ENV_PAYLOAD_LOADER) { - mtrr_use_temp_range(base, bios_size, type); - } else { - int mtrr = get_free_var_mtrr(); - - if (mtrr == -1) - return; - - set_var_mtrr(mtrr, base, bios_size, type); - } + fast_spi_enable_cache_range(base, bios_size); /* Check if caching is needed for extended bios region if supported */ fast_spi_cache_ext_bios_window(); -- cgit v1.2.3