From 5391e554e190d746ae54d09cd97c313736a04027 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Fri, 2 Jun 2017 12:16:04 -0500 Subject: soc/intel/common/block: add bios caching to fast spi module MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add fast_spi_cache_bios_region() that sets up a variable MTRR as write-protect covering the fast spi BIOS region. Change-Id: I282c5173cc655004daf16ea2e85423aaded3648d Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/20019 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Subrata Banik Reviewed-by: Philippe Mathieu-Daudé --- src/soc/intel/common/block/fast_spi/fast_spi.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'src/soc/intel/common/block/fast_spi/fast_spi.c') diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 603af16881..a53499eba6 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -18,8 +18,10 @@ #include #include #include +#include #include #include +#include #include #include #include @@ -175,6 +177,29 @@ size_t fast_spi_get_bios_region(size_t *bios_size) return bios_start; } +void fast_spi_cache_bios_region(void) +{ + int mtrr; + size_t bios_size; + uint32_t alignment; + + mtrr = get_free_var_mtrr(); + + if (mtrr == -1) + return; + + /* Only the IFD BIOS region is memory mapped (at top of 4G) */ + fast_spi_get_bios_region(&bios_size); + + if (!bios_size) + return; + + /* Round to power of two */ + alignment = 1 << (log2_ceil(bios_size)); + bios_size = ALIGN_UP(bios_size, alignment); + set_var_mtrr(mtrr, 4ULL*GiB - bios_size, bios_size, MTRR_TYPE_WRPROT); +} + /* * Program temporary BAR for SPI in case any of the stages before ramstage need * to access FAST_SPI MMIO regs. Ramstage will assign a new BAR during PCI -- cgit v1.2.3