From 2cc66916e5d5d5b0d2e92e180bae7ac64d30cbac Mon Sep 17 00:00:00 2001 From: Sridhar Siricilla Date: Sat, 31 Aug 2019 11:20:34 +0530 Subject: soc/intel/common/block/cse: Move me_read_config32() to common code me_read_config32() is defined in multiple places, move it to common location. Also, this function is usually used for reading HFSTS registers, hence move the HFSTS register definitions to common location. Also add a funtion to check if the CSE device has been enabled in the devicetree and it is visible on the bus. This API can be used by the caller to check before initiating any HECI communication. TEST=Verified reading HFSTS registers on CML RVP & Hatch board Change-Id: Icdbfb6b30a007d469b5e018a313c14586addb130 Signed-off-by: Sridhar Siricilla Signed-off-by: Rizwan Qureshi Reviewed-on: https://review.coreboot.org/c/coreboot/+/35225 Reviewed-by: Subrata Banik Reviewed-by: Aamir Bohra Reviewed-by: V Sowmya Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/cse/cse.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'src/soc/intel/common/block/cse') diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 9520242d2e..1671970a19 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -503,6 +503,28 @@ int heci_reset(void) return 0; } +bool is_cse_enabled(void) +{ + const struct device *cse_dev = pcidev_path_on_root(PCH_DEVFN_CSE); + + if (!cse_dev || !cse_dev->enabled) { + printk(BIOS_WARNING, "HECI: No CSE device\n"); + return false; + } + + if (pci_read_config16(PCH_DEV_CSE, PCI_VENDOR_ID) == 0xFFFF) { + printk(BIOS_WARNING, "HECI: CSE device is hidden\n"); + return false; + } + + return true; +} + +uint32_t me_read_config32(int offset) +{ + return pci_read_config32(PCH_DEV_CSE, offset); +} + #if ENV_RAMSTAGE static void update_sec_bar(struct device *dev) -- cgit v1.2.3