From a1061639d2d17886032df86c0f9b21e44b9e9818 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Wed, 1 Jul 2020 09:32:18 -0600 Subject: soc/intel/common: Only touch Time Window Tau bits in supported SoCs The Time Window Tau bits are only supported by Comet Lake/Cannon Lake onwards, so skip setting those bits for earlier SoCs. Change-Id: Iff899ee8280a9b9bbcea57d4e98b92d5410be21d Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/42979 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh Reviewed-by: Sumeet R Pawnikar --- src/soc/intel/common/block/cpu/cpulib.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'src/soc/intel/common/block/cpu') diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index e4ab664285..0cebe329c0 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -272,9 +272,17 @@ void configure_tcc_thermal_target(void) wrmsr(MSR_TEMPERATURE_TARGET, msr); } - msr = rdmsr(MSR_TEMPERATURE_TARGET); + /* + * SoCs prior to Comet Lake/Cannon Lake do not support the time window + * bits, so return early. + */ + if (CONFIG(SOC_INTEL_APOLLOLAKE) || CONFIG(SOC_INTEL_SKYLAKE) || + CONFIG(SOC_INTEL_KABYLAKE) || CONFIG(SOC_INTEL_BRASWELL) || + CONFIG(SOC_INTEL_BROADWELL)) + return; /* Time Window Tau Bits [6:0] */ + msr = rdmsr(MSR_TEMPERATURE_TARGET); msr.lo &= ~0x7f; msr.lo |= 0xe6; /* setting 100ms thermal time window */ wrmsr(MSR_TEMPERATURE_TARGET, msr); -- cgit v1.2.3