From 860c68449da9a6752fedb752cacdf0ac8bd6a61d Mon Sep 17 00:00:00 2001 From: Shreesh Chhabbi Date: Thu, 3 Dec 2020 15:06:20 -0800 Subject: src/soc/intel: Add support for CAR_HAS_SF_MASKS and select for TGL Program IA32_CR_SF_QOS_MASK_x MSRs under CAR_HAS_SF_MASKS config option. Select CAR_HAS_SF_MASKS for Tigerlake. During CAR teardown code, MSRs IA32_L3_MASK_x & IA32_CR_SF_QOS_MASK_x are not being reset to default as per the doc NEM-Enhanced-Mode-Whitepaper-Tigerlake-draft-WW46.5. Resetting the value of IA32_PQR_ASSOC[32:33] to 00b is sufficient. Bug=b:171601324 BRANCH=volteer Test=Build and boot to ChromeOS on Delbin. Signed-off-by: Shreesh Chhabbi Change-Id: Iabf7f387fb5887aca10158788599452c3f2df7e8 Signed-off-by: Shreesh Chhabbi Reviewed-on: https://review.coreboot.org/c/coreboot/+/48286 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Tim Wawrzynczak --- src/soc/intel/common/block/cpu/Kconfig | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/soc/intel/common/block/cpu/Kconfig') diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 912760e217..2b630d0cdf 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -51,6 +51,14 @@ config INTEL_CAR_NEM_ENHANCED ENHANCED NEM guarantees that modified data is always kept in cache while clean data is replaced. +config CAR_HAS_SF_MASKS + bool + depends on INTEL_CAR_NEM_ENHANCED + help + In the case of non-inclusive cache architecture Snoop Filter MSR + IA32_L3_SF_MASK_x programming is required along with the data ways. + This is applicable for TGL and beyond. + config COS_MAPPED_TO_MSB bool depends on INTEL_CAR_NEM_ENHANCED -- cgit v1.2.3