From 2c2706cceff42e019dcf0bb64fafd754ace8b707 Mon Sep 17 00:00:00 2001 From: Sridhar Siricilla Date: Tue, 25 Jan 2022 00:15:17 +0530 Subject: soc/intel/common: Add support to control coreboot and Intel SoC features The patch adds a framework to control coreboot and Intel SoC features dynamically. BIOS reads control information from OEM Section in the Descriptor Region and control the developer selected features. With the feature, debug team can control the selected SoC and coreboot features without rebuilding coreboot. In order to enable the feature, SOC_INTEL_COMMON_BLOCK_DEBUG_FEATURE has to be selcted from mainboard. The OEM section starts from offset:0xf00 till end of the Descriptor Region(0xfff). BUG=b:153410586 BRANCH=None TEST=Verified CSE firmware update functionality on brya Signed-off-by: Sridhar Siricilla Change-Id: I5ba40926bd9ad909654f152e48cdd648b28afd62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61380 Tested-by: build bot (Jenkins) Reviewed-by: Ronak Kanabar Reviewed-by: Maulik V Vaghela --- .../common/basecode/include/intelbasecode/debug_feature.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 src/soc/intel/common/basecode/include/intelbasecode/debug_feature.h (limited to 'src/soc/intel/common/basecode/include/intelbasecode') diff --git a/src/soc/intel/common/basecode/include/intelbasecode/debug_feature.h b/src/soc/intel/common/basecode/include/intelbasecode/debug_feature.h new file mode 100644 index 0000000000..fabf27ddd8 --- /dev/null +++ b/src/soc/intel/common/basecode/include/intelbasecode/debug_feature.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE_H +#define SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE_H + +#include + +/* + * Reads OEM Section area in the Descriptor Region and + * populates pre_mem_debug structure. + */ +uint8_t pre_mem_debug_init(void); + +#endif -- cgit v1.2.3