From c1645faeff3f128efcf411a98772ac9d327fc7aa Mon Sep 17 00:00:00 2001
From: Subrata Banik <subrata.banik@intel.com>
Date: Fri, 5 Aug 2016 18:25:55 +0530
Subject: soc/intel/common: Add support for serial console based ACPI debug

This patch enables serial debug functionality for ASL code based on
UART type(legacy/LPSS).

From Skylake onwards all Intel platform uses LPSS based UART for serial
console hence provide option to redirect ASL log over LPSS UART.

Example:
Name (OBJ, 0x12)
APRT (OBJ)
APRT ("CORE BOOT")

Output:
0x12
CORE BOOT

BUG=none
BRANCH=none
TEST=Built and boot kunimitsu to ensure to be able to get ASL console log.

Change-Id: I18c65654b8eb1ac27af1f283d413376fd79d47db
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/16070
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/soc/intel/common/acpi/acpi_debug.asl | 113 +++++++++++++++++++++++++++++++
 1 file changed, 113 insertions(+)
 create mode 100644 src/soc/intel/common/acpi/acpi_debug.asl

(limited to 'src/soc/intel/common/acpi/acpi_debug.asl')

diff --git a/src/soc/intel/common/acpi/acpi_debug.asl b/src/soc/intel/common/acpi/acpi_debug.asl
new file mode 100644
index 0000000000..5b686f2375
--- /dev/null
+++ b/src/soc/intel/common/acpi/acpi_debug.asl
@@ -0,0 +1,113 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#if IS_ENABLED(CONFIG_ACPI_CONSOLE)
+
+#include <soc/iomap.h>
+
+Name (UFLG, IS_ENABLED(CONFIG_CONSOLE_SERIAL))
+
+Method (LURT, 1, Serialized)
+{
+	If (LEqual(Arg0, 0)) { /* 0 = 0x3f8 */
+		Store (0x3f8, Local0)
+	} ElseIf (LEqual(Arg0, 1)) { /* 1 = 0x2f8 */
+		Store (0x2f8, Local0)
+	} ElseIf (LEqual(Arg0, 2)) { /* 2 = 0x3e8 */
+		Store (0x3e8, Local0)
+	} ElseIf (LEqual(Arg0, 3)) { /* 3 = 0x2e8 */
+		Store (0x2e8, Local0)
+	}
+	Return (Local0)
+}
+
+Method (APRT, 1, Serialized)
+{
+	Name(OPDT, 0)
+	Name(INDX, 0)
+	Name(LENG, 0)
+	Name(ADBG, Buffer(256) {0})
+
+	If (LEqual(ObjectType(Arg0), 1)) { /* Integer */
+		ToHexString(Arg0, ADBG)
+	} ElseIf (LEqual(ObjectType(Arg0), 2)) { /* String */
+		Store(Arg0, ADBG)
+	} ElseIf (LEqual(ObjectType(Arg0), 3)) { /* Buffer */
+		ToHexString(Arg0, ADBG)
+	} Else {
+		Store("This type of object is not supported", ADBG)
+	}
+
+	While (LNotEqual(DeRefOf(Index(ADBG, INDX)), 0))
+	{
+		Increment (INDX)
+	}
+	Store (INDX, LENG) /* Length of the String */
+
+#if CONFIG_DRIVERS_UART_8250MEM_32
+	OperationRegion (UBAR, SystemMemory, UART_DEBUG_BASE_ADDRESS, 24)
+	Field (UBAR, AnyAcc, NoLock, Preserve)
+	{
+		TDR, 32,	/* Transmit Data Register BAR + 0x000 */
+		IER, 32,	/* Interrupt Enable Register BAR + 0x004 */
+		IIR, 32,	/* Interrupt Identification Register BAR + 0x008 */
+		LCR, 32,	/* Line Control Register BAR + 0x00C */
+		MCR, 32,	/* Modem Control Register BAR + 0x010 */
+		LSR, 32	/* Line Status Register BAR + 0x014 */
+	}
+#else
+	OperationRegion (UBAR, SystemIO, LURT (CONFIG_UART_FOR_CONSOLE), 6)
+	Field (UBAR, ByteAcc, NoLock, Preserve)
+	{
+		TDR, 8,	/* Transmit Data Register IO Port + 0x0 */
+		IER, 8,	/* Interrupt Enable Register IO Port + 0x1 */
+		IIR, 8,	/* Interrupt Identification Register IO Port + 0x2 */
+		LCR, 8,	/* Line Control Register IO Port + 0x3 */
+		MCR, 8,	/* Modem Control Register IO Port + 0x4 */
+		LSR, 8	/* Line Status Register IO Port + 0x5 */
+	}
+#endif
+
+	If (LEqual(UFLG, 0)) {
+		/* Enable Baud Rate Divisor Latch, Set Word length to 8 bit*/
+		Store (0x83, LCR)
+		Store (0x01, IIR)
+		Store (0x03, MCR)
+
+		/* Configure baud rate to 115200 */
+		Store (0x01, TDR)
+		Store (0x00, IER)
+		Store (0x03, LCR) /* Disable Baud Rate Divisor Latch */
+
+		Increment (UFLG)
+	}
+	Store (0x00, INDX)
+	While (LLess (INDX, LENG))
+	{
+		/* Wait for the transmitter t to be ready */
+		While (1)
+		{
+			And (LSR, 0x20, OPDT)
+			If (LNotEqual(OPDT, 0))
+			{
+				Break
+			}
+		}
+		Store (DeRefOf (Index (ADBG, INDX)), TDR)
+		Increment(INDX)
+	}
+} /* End of APRT */
+
+#endif
-- 
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