From 9d9a121fa0cc0a5b303aaf377ce2a8e426ef0d3a Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Wed, 19 Apr 2017 10:02:27 -0500 Subject: soc/intel/common: provide default tis_plat_irq_status() implementation On Intel platforms utilizing the CR50 TPM the interrupts are routed to GPIOs connected to the GPE blocks. Therefore, provide a common implementation for tis_plat_irq_status() to reduce code duplication. This code could be further extended to not be added based on MAINBOARD_HAS_TPM_CR50, but that's all that's using it for now. Change-Id: I955df0a536408b2ccd07146893337c53799e243f Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/19369 Reviewed-by: Furquan Shaikh Reviewed-by: Duncan Laurie Tested-by: build bot (Jenkins) --- src/soc/intel/common/Makefile.inc | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/soc/intel/common/Makefile.inc') diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index acfd0548b2..b01fc8a70e 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -37,6 +37,11 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_NHLT) += nhlt.c smm-$(CONFIG_SOC_INTEL_COMMON_SMI) += smihandler.c +bootblock-$(CONFIG_MAINBOARD_HAS_TPM_CR50) += tpm_tis.c +verstage-$(CONFIG_MAINBOARD_HAS_TPM_CR50) += tpm_tis.c +romstage-$(CONFIG_MAINBOARD_HAS_TPM_CR50) += tpm_tis.c +ramstage-$(CONFIG_MAINBOARD_HAS_TPM_CR50) += tpm_tis.c + # Create and add the MRC cache to the cbfs image ifneq ($(CONFIG_CHROMEOS),y) $(obj)/mrc.cache: $(obj)/config.h -- cgit v1.2.3