From ed3e6b8b946e0c5fbc417551750da67c284eaf8b Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Tue, 26 Sep 2017 13:56:24 -0700 Subject: soc/intel/cannonlake: Disable CPU ratio override Disable CPU Ratio override as input to FSP Memory init. Change-Id: I4a1df15c619038f17c1bef5b7f53d322e352c56b Signed-off-by: Lijian Zhao Reviewed-on: https://review.coreboot.org/21709 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/cannonlake/romstage/romstage.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/soc/intel/cannonlake') diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index a9ad1d804e..1775cae779 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -86,6 +86,8 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) m_cfg->PcieRpEnableMask = mask; m_cfg->PrmrrSize = config->PrmrrSize; m_cfg->EnableC6Dram = config->enable_c6dram; + /* Disable Cpu Ratio Override temporary. */ + m_cfg->CpuRatio = 0; } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -- cgit v1.2.3