From c4f8fbdb11ca891e844903643a44cfa6c5bb8871 Mon Sep 17 00:00:00 2001 From: Michael Niewöhner Date: Sat, 19 Dec 2020 14:11:32 +0100 Subject: soc/intel/cnl: add panel and backlight configuration code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add code for panel and backlight configuration. Tested successfully with libgfxinit on Clevo L141CU. Change-Id: If619b28478b4b0d18f28f318c16336e0de76e129 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/48749 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier Reviewed-by: Nico Huber --- src/soc/intel/cannonlake/Makefile.inc | 1 + src/soc/intel/cannonlake/chip.h | 5 +++ src/soc/intel/cannonlake/graphics.c | 63 +++++++++++++++++++++++++++++++++++ 3 files changed, 69 insertions(+) create mode 100644 src/soc/intel/cannonlake/graphics.c (limited to 'src/soc/intel/cannonlake') diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 96f1f97d0e..e0605817ae 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -36,6 +36,7 @@ ramstage-y += cpu.c ramstage-y += elog.c ramstage-y += finalize.c ramstage-y += fsp_params.c +ramstage-y += graphics.c ramstage-y += gspi.c ramstage-y += i2c.c ramstage-y += lockdown.c diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 492ebca9c2..2727aa22a7 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -437,6 +438,10 @@ struct soc_intel_cannonlake_config { * Only override CPU flex ratio if don't want to boot with non-turbo max. */ uint8_t cpu_ratio_override; + + struct i915_gpu_panel_config panel_cfg; + + struct i915_gpu_controller_info gfx; }; typedef struct soc_intel_cannonlake_config config_t; diff --git a/src/soc/intel/cannonlake/graphics.c b/src/soc/intel/cannonlake/graphics.c new file mode 100644 index 0000000000..93a84c293a --- /dev/null +++ b/src/soc/intel/cannonlake/graphics.c @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void graphics_soc_panel_init(struct device *dev) +{ + const struct soc_intel_cannonlake_config *conf = dev->chip_info; + const struct i915_gpu_panel_config *panel_cfg; + const struct resource *mmio_res; + void *mmio; + uint32_t reg32; + unsigned int pwm_period, pwm_polarity, pwm_duty; + + if (!conf) + return; + + panel_cfg = &conf->panel_cfg; + + mmio_res = probe_resource(dev, PCI_BASE_ADDRESS_0); + if (!mmio_res || !mmio_res->base) + return; + mmio = (void *)(uintptr_t)mmio_res->base; + + /* Panel timings */ + + reg32 = ((DIV_ROUND_UP(panel_cfg->cycle_delay_ms, 100) + 1) & 0x1f) << 4; + reg32 |= PANEL_POWER_RESET; + write32(mmio + PCH_PP_CONTROL, reg32); + + reg32 = ((panel_cfg->up_delay_ms * 10) & 0x1fff) << 16; + reg32 |= (panel_cfg->backlight_on_delay_ms * 10) & 0x1fff; + write32(mmio + PCH_PP_ON_DELAYS, reg32); + + reg32 = ((panel_cfg->down_delay_ms * 10) & 0x1fff) << 16; + reg32 |= (panel_cfg->backlight_off_delay_ms * 10) & 0x1fff; + write32(mmio + PCH_PP_OFF_DELAYS, reg32); + + /* Backlight */ + if (panel_cfg->backlight_pwm_hz) { + pwm_polarity = panel_cfg->backlight_polarity ? BXT_BLC_PWM_POLARITY : 0; + pwm_period = DIV_ROUND_CLOSEST(CONFIG_CPU_XTAL_HZ, panel_cfg->backlight_pwm_hz); + pwm_duty = DIV_ROUND_CLOSEST(pwm_period, 2); /* Start with 50 % */ + + write32(mmio + BXT_BLC_PWM_FREQ(0), pwm_period); + write32(mmio + BXT_BLC_PWM_CTL(0), pwm_polarity); + write32(mmio + BXT_BLC_PWM_DUTY(0), pwm_duty); + } +} + +const struct i915_gpu_controller_info * +intel_igd_get_controller_info(const struct device *const dev) +{ + const struct soc_intel_cannonlake_config *const chip = dev->chip_info; + return &chip->gfx; +} -- cgit v1.2.3