From c126084bc53e0f74f6085f4f84b5bc387d701a4f Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Tue, 23 Apr 2019 15:18:51 -0600 Subject: soc/intel: Add GPI interrupt config register offset info Add the offset information for GPI interrupt status and enable register in the pad_community structure. Populate the concerned information for individual SoCs. This offset information is required to clear the interrupt configuration during the bootup. BUG=b:130593883 BRANCH=None TEST=Ensure that the interrupt configuration are cleared during bootup. Ensured that the system boots to ChromeOS. Change-Id: I8af877a734e8d49b700d720b736da8764985a8f8 Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/32446 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/cannonlake/gpio.c | 10 ++++++++++ src/soc/intel/cannonlake/gpio_cnp_h.c | 10 ++++++++++ src/soc/intel/cannonlake/include/soc/gpio_defs.h | 2 ++ src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h | 2 ++ 4 files changed, 24 insertions(+) (limited to 'src/soc/intel/cannonlake') diff --git a/src/soc/intel/cannonlake/gpio.c b/src/soc/intel/cannonlake/gpio.c index 30ee9398d5..dd514643d7 100644 --- a/src/soc/intel/cannonlake/gpio.c +++ b/src/soc/intel/cannonlake/gpio.c @@ -85,6 +85,8 @@ static const struct pad_community cnl_communities[] = { .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -101,6 +103,8 @@ static const struct pad_community cnl_communities[] = { .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -117,6 +121,8 @@ static const struct pad_community cnl_communities[] = { .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -133,6 +139,8 @@ static const struct pad_community cnl_communities[] = { .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -149,6 +157,8 @@ static const struct pad_community cnl_communities[] = { .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, diff --git a/src/soc/intel/cannonlake/gpio_cnp_h.c b/src/soc/intel/cannonlake/gpio_cnp_h.c index d59dea5cbc..102444a9f8 100644 --- a/src/soc/intel/cannonlake/gpio_cnp_h.c +++ b/src/soc/intel/cannonlake/gpio_cnp_h.c @@ -87,6 +87,8 @@ static const struct pad_community cnl_communities[] = { .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -103,6 +105,8 @@ static const struct pad_community cnl_communities[] = { .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -119,6 +123,8 @@ static const struct pad_community cnl_communities[] = { .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -135,6 +141,8 @@ static const struct pad_community cnl_communities[] = { .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -151,6 +159,8 @@ static const struct pad_community cnl_communities[] = { .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_defs.h index 8a944b1b48..5c12e4cb67 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_defs.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_defs.h @@ -246,6 +246,8 @@ #define GPE_DW_SHIFT 8 #define GPE_DW_MASK 0xfff00 #define HOSTSW_OWN_REG_0 0xb0 +#define GPI_INT_STS_0 0x100 +#define GPI_INT_EN_0 0x120 #define GPI_SMI_STS_0 0x180 #define GPI_SMI_EN_0 0x1A0 #define PAD_CFG_BASE 0x600 diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h index e77dbf88cf..d03723dae1 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h @@ -320,6 +320,8 @@ #define GPE_DW_SHIFT 8 #define GPE_DW_MASK 0xfff00 #define HOSTSW_OWN_REG_0 0xc0 +#define GPI_INT_STS_0 0x100 +#define GPI_INT_EN_0 0x120 #define GPI_SMI_STS_0 0x180 #define GPI_SMI_EN_0 0x1A0 #define PAD_CFG_BASE 0x600 -- cgit v1.2.3