From b4a68a5a28684b99657ae94b9bcb745ae2023863 Mon Sep 17 00:00:00 2001
From: Edward O'Callaghan <quasisec@google.com>
Date: Sun, 15 Dec 2019 13:30:38 +1100
Subject: src/soc/intel/cannonlake: Bump MAX_CPU from 8->12

This impacts boards:
 hatch (&variants) and drallion.

Some variants like Puff can have up to 12 cores. coreboot should take
the min() where MAX_CPU is the upper bound.

Further to that, boards themseleves shouldn't be setting the MAX_CPUS,
the chipset should be and so do that.

BRANCH=none
BUG=b:146255011
TEST=./util/abuild/abuild -p none -t google/hatch -x -a

Change-Id: I284d027886f662ebb8414ea92540916ed19bc797
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
---
 src/soc/intel/cannonlake/Kconfig | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'src/soc/intel/cannonlake')

diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 6d635ade3d..8820508259 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -108,6 +108,10 @@ config CPU_SPECIFIC_OPTIONS
 	select FSP_T_XIP if FSP_CAR
 	select HECI_DISABLE_USING_SMM if !SOC_INTEL_COFFEELAKE && !SOC_INTEL_WHISKEYLAKE && !SOC_INTEL_COMETLAKE
 
+config MAX_CPUS
+	int
+	default 12
+
 config DCACHE_RAM_BASE
 	default 0xfef00000
 
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