From b2a442ed5915e17b057efcfb81b5c826cafd63f3 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 21 Oct 2021 10:40:23 +0200 Subject: soc/intel/cannonlake: Fix PEG1 _PRT generation Some weird things happen inside FSP and the routing is not correctly applied, with PIN D being used but lacking a proper routing in ACPI. To work around this issue generate _PRT for all 4 INT pins. Change-Id: I5be6e4514f8c6a47bb887d9f9b95181c9f426a51 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/58517 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Tim Wawrzynczak --- src/soc/intel/cannonlake/fsp_params.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/soc/intel/cannonlake') diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index f22e39d442..32c5cbb8c6 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -44,6 +44,12 @@ static const struct slot_irq_constraints irq_constraints[] = { FIXED_INT_PIRQ(SA_DEVFN_PEG0, PCI_INT_A, PIRQ_A), FIXED_INT_PIRQ(SA_DEVFN_PEG1, PCI_INT_B, PIRQ_B), FIXED_INT_PIRQ(SA_DEVFN_PEG2, PCI_INT_C, PIRQ_C), + /* + * It looks like FSP does not apply this mapping properly to + * the PEG functions. The PINx to PIRQx mapping needs to be there + * in ACPI however in case PIN D is used. + */ + FIXED_INT_PIRQ(PCI_DEVFN(SA_DEV_SLOT_PEG, 3), PCI_INT_D, PIRQ_D), }, }, { -- cgit v1.2.3