From a06f55b8e4a4e51815d654f6125a60c0db3550e4 Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Wed, 4 Oct 2017 23:08:55 -0700 Subject: soc/intel/cannonlake: Enable MRC cache MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable MRC cache by default. TEST=Warm reset and check coreboot serial log, MRC related log can be seen. Change-Id: I76ece361867737c01cc848c24d8893d43a3d292e Signed-off-by: Lijian Zhao Reviewed-on: https://review.coreboot.org/21892 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer Reviewed-by: Aaron Durbin --- src/soc/intel/cannonlake/Kconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/soc/intel/cannonlake') diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 9153b04985..b60d3d54a6 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -15,6 +15,7 @@ config CPU_SPECIFIC_OPTIONS select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select C_ENVIRONMENT_BOOTBLOCK + select CACHE_MRC_SETTINGS select COMMON_FADT select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select GENERIC_GPIO_LIB @@ -26,6 +27,7 @@ config CPU_SPECIFIC_OPTIONS select INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ADD_VBT_DATA_FILE if RUN_FSP_GOP select IOAPIC + select MRC_SETTINGS_PROTECT select PARALLEL_MP select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_0 -- cgit v1.2.3