From 98d580b8fbd2cf9ccafc2dd0ad48ae7d5ba86186 Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Tue, 29 Dec 2020 11:17:28 -0700 Subject: soc/intel/cannonlake: Allow RP#1 usage for ClkSrc 0 is converted to not used, so use a special value to allow using PCIe root port #1. Change-Id: I2d64afc9bb4627913492edad8f36566e7fb18166 Signed-off-by: Jeremy Soller Signed-off-by: Tim Crawford Reviewed-on: https://review.coreboot.org/c/coreboot/+/49172 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/soc/intel/cannonlake/fsp_params.c | 2 ++ src/soc/intel/cannonlake/include/soc/pch.h | 2 ++ 2 files changed, 4 insertions(+) (limited to 'src/soc/intel/cannonlake') diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index dd9c806039..075c3283cc 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -349,6 +349,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) { if (config->PcieClkSrcUsage[i] == 0) config->PcieClkSrcUsage[i] = PCIE_CLK_NOTUSED; + else if (config->PcieClkSrcUsage[i] == PCIE_CLK_RP0) + config->PcieClkSrcUsage[i] = 0; } memcpy(params->PcieClkSrcUsage, config->PcieClkSrcUsage, sizeof(config->PcieClkSrcUsage)); diff --git a/src/soc/intel/cannonlake/include/soc/pch.h b/src/soc/intel/cannonlake/include/soc/pch.h index 0fbb98533a..e4fd36de33 100644 --- a/src/soc/intel/cannonlake/include/soc/pch.h +++ b/src/soc/intel/cannonlake/include/soc/pch.h @@ -10,5 +10,7 @@ #define PCIE_CLK_NOTUSED 0xFF #define PCIE_CLK_LAN 0x70 #define PCIE_CLK_FREE 0x80 +/* Converted to 0, allows 0 to be notused */ +#define PCIE_CLK_RP0 0xFE #endif -- cgit v1.2.3