From 5d805f64f95dd07b5b78abde84d567ac9bd6a1d6 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 23 Aug 2021 13:21:31 +0200 Subject: soc/intel/cannonlake: Fix PCH-H IRQ constraints Cannon Point PCH-H does not implement the eMMC, I2C4 and I2C5 devices. Guard the IRQ constraints for these devices to prevent FSP assertions. Tested on Prodrive Hermes, debug FSP builds no longer fail to boot. Change-Id: I58674d1c3c5fe4535c022020674d48d6a5315bf9 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/57092 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/cannonlake/fsp_params.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/soc/intel/cannonlake') diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 2c82c38ca4..dd5f197a19 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -74,7 +74,9 @@ static const struct slot_irq_constraints irq_constraints[] = { .slot = PCH_DEV_SLOT_THERMAL, .fns = { ANY_PIRQ(PCH_DEVFN_THERMAL), +#if !CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) ANY_PIRQ(PCH_DEVFN_UFS), +#endif DIRECT_IRQ(PCH_DEVFN_GSPI2), }, }, @@ -122,17 +124,21 @@ static const struct slot_irq_constraints irq_constraints[] = { { .slot = PCH_DEV_SLOT_SIO2, .fns = { +#if !CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) DIRECT_IRQ(PCH_DEVFN_I2C4), DIRECT_IRQ(PCH_DEVFN_I2C5), +#endif DIRECT_IRQ(PCH_DEVFN_UART2), }, }, +#if !CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) { .slot = PCH_DEV_SLOT_STORAGE, .fns = { ANY_PIRQ(PCH_DEVFN_EMMC), }, }, +#endif #if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) { .slot = PCH_DEV_SLOT_PCIE_2, -- cgit v1.2.3