From 10ae1cf2cda38e681849dcc9e6e86ee3330a8b17 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sun, 11 Oct 2020 14:05:32 +0200 Subject: {cpu,soc}/intel: deduplicate cpu code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move a whole bunch of copy-pasta code from soc/intel/{bdw,skl,cnl,icl, tgl,ehl,jsl,adl} and cpu/intel/{hsw,model_*} to cpu/intel/common. This change just moves the code. Rework is done in CB:46588. Change-Id: Ib0cc834de8492d59c423317598e1c11847a0b1ab Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/46274 Reviewed-by: Felix Singer Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/cpu.c | 41 ------------------------------ src/soc/intel/cannonlake/include/soc/msr.h | 1 - 2 files changed, 42 deletions(-) (limited to 'src/soc/intel/cannonlake') diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 0622034217..b6b921a29b 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -83,29 +83,6 @@ static void configure_misc(void) wrmsr(MSR_POWER_CTL, msr); } -static void enable_lapic_tpr(void) -{ - msr_t msr; - - msr = rdmsr(MSR_PIC_MSG_CONTROL); - msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ - wrmsr(MSR_PIC_MSG_CONTROL, msr); -} - -static void configure_dca_cap(void) -{ - uint32_t feature_flag; - msr_t msr; - - /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */ - feature_flag = cpu_get_feature_flags_ecx(); - if (feature_flag & CPUID_DCA) { - msr = rdmsr(IA32_PLATFORM_DCA_CAP); - msr.lo |= 1; - wrmsr(IA32_PLATFORM_DCA_CAP, msr); - } -} - /* * The emulated ACPI timer allows replacing of the ACPI timer * (PM1_TMR) to have no impart on the system. @@ -129,24 +106,6 @@ static void enable_pm_timer_emulation(void) wrmsr(MSR_EMULATE_PM_TIMER, msr); } - -static void set_energy_perf_bias(u8 policy) -{ - msr_t msr; - int ecx; - - /* Determine if energy efficient policy is supported. */ - ecx = cpuid_ecx(0x6); - if (!(ecx & (1 << 3))) - return; - - /* Energy Policy is bits 3:0 */ - msr = rdmsr(IA32_ENERGY_PERF_BIAS); - msr.lo &= ~0xf; - msr.lo |= policy & 0xf; - wrmsr(IA32_ENERGY_PERF_BIAS, msr); -} - static void configure_c_states(void) { msr_t msr; diff --git a/src/soc/intel/cannonlake/include/soc/msr.h b/src/soc/intel/cannonlake/include/soc/msr.h index 57d109b318..1c902d5abb 100644 --- a/src/soc/intel/cannonlake/include/soc/msr.h +++ b/src/soc/intel/cannonlake/include/soc/msr.h @@ -5,7 +5,6 @@ #include -#define MSR_PIC_MSG_CONTROL 0x2e #define MSR_VR_CURRENT_CONFIG 0x601 #define MSR_PL3_CONTROL 0x615 #define MSR_VR_MISC_CONFIG2 0x636 -- cgit v1.2.3