From 03ed5bff5cb13118b203b34b18e05694e713a30a Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Thu, 16 Jul 2020 16:31:32 -0600 Subject: soc/intel/cannonlake: Move tco_configure to bootblock Similar to CB:43313 (SHA bb50c672278), it seems possible for the same problem to come up on cannonlake. Again, it should be harmless to configure the TCO device earlier in the boot flow. Signed-off-by: Tim Wawrzynczak Change-Id: Ib8883d27b2a0994a67ec5e044a692a2e853fd680 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43538 Reviewed-by: Furquan Shaikh Reviewed-by: Aaron Durbin Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/bootblock/bootblock.c | 4 ++++ src/soc/intel/cannonlake/romstage/pch.c | 4 ---- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'src/soc/intel/cannonlake') diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c index de32fcda3d..a72b66e75f 100644 --- a/src/soc/intel/cannonlake/bootblock/bootblock.c +++ b/src/soc/intel/cannonlake/bootblock/bootblock.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -65,4 +66,7 @@ void bootblock_soc_init(void) gpi_clear_int_cfg(); report_platform_info(); bootblock_pch_init(); + + /* Program TCO_BASE_ADDRESS and TCO Timer Halt */ + tco_configure(); } diff --git a/src/soc/intel/cannonlake/romstage/pch.c b/src/soc/intel/cannonlake/romstage/pch.c index c85bdd667f..f94d611abe 100644 --- a/src/soc/intel/cannonlake/romstage/pch.c +++ b/src/soc/intel/cannonlake/romstage/pch.c @@ -1,14 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include void romstage_pch_init(void) { - /* Program TCO_BASE_ADDRESS and TCO Timer Halt */ - tco_configure(); - /* Program SMBUS_BASE_ADDRESS and enable it */ smbus_common_init(); } -- cgit v1.2.3