From 399c022a8c6cba7ad6d75fdf377a690395877611 Mon Sep 17 00:00:00 2001
From: Lijian Zhao <lijian.zhao@intel.com>
Date: Tue, 11 Jul 2017 12:33:22 -0700
Subject: soc/intel/cannonlake: Add postcar stage support

Initialize postcar frame once finish FSP memoryinit

Change-Id: I888d471fa620b7fc9f8975524a31f662e1fc5079
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/soc/intel/cannonlake/uart.c | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'src/soc/intel/cannonlake/uart.c')

diff --git a/src/soc/intel/cannonlake/uart.c b/src/soc/intel/cannonlake/uart.c
index 6f5fb6d7e9..dd121b04a4 100644
--- a/src/soc/intel/cannonlake/uart.c
+++ b/src/soc/intel/cannonlake/uart.c
@@ -13,6 +13,8 @@
  * GNU General Public License for more details.
  */
 
+#define __SIMPLE_DEVICE__
+
 #include <assert.h>
 #include <console/uart.h>
 #include <device/pci_def.h>
@@ -60,8 +62,10 @@ void pch_uart_init(void)
 	gpio_configure_pads(p->pads, ARRAY_SIZE(p->pads));
 }
 
+#if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM)
 uintptr_t uart_platform_base(int idx)
 {
 	/* We can only have one serial console at a time */
 	return UART_DEBUG_BASE_ADDRESS;
 }
+#endif
-- 
cgit v1.2.3