From f5c0d612966d1ab3e8c2f1d1ae1de9ae2438bbab Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Wed, 14 Aug 2019 13:02:41 +0300 Subject: intel/smm: Provide common smm_relocation_params MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Pull in all copies of smm_relocation_params structs defined for intel platforms. Pull in all the inlined MSR accessors to the header file. Change-Id: I39c6cffee95433aea1a3c783b869eedfff094413 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34840 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/cannonlake/smmrelocate.c | 11 ----------- 1 file changed, 11 deletions(-) (limited to 'src/soc/intel/cannonlake/smmrelocate.c') diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c index 6680bf3717..54e2f927b8 100644 --- a/src/soc/intel/cannonlake/smmrelocate.c +++ b/src/soc/intel/cannonlake/smmrelocate.c @@ -31,20 +31,9 @@ #include #include #include -#include #include #include "chip.h" -/* This gets filled in and used during relocation. */ -static struct smm_relocation_params smm_reloc_params; - -static inline void write_smrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); -} static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, -- cgit v1.2.3