From 9b50a57e4343ce77b8ae1aaca5a3866599056456 Mon Sep 17 00:00:00 2001
From: Lijian Zhao <lijian.zhao@intel.com>
Date: Thu, 21 Dec 2017 13:40:07 -0800
Subject: soc/intel/cannonlake: Program DMI PCR settings

According to CNL PCH BIOS spec (570374) 2.4.1, DMI cycle decoding needs
to be programmed before it gets locked. Update lpc programming to add
decode programming on DMI side as well. Also enabled io port 0x200
decoding by default.

BUG=b.70765863
TEST=Apply changes and add chromeos EC decoding in mainboard
devicetree.cb, then read back IO port in depthcharge cli and check
that return is not zero.

Change-Id: I6b8f393c92cbd0632fed86212ae384ff53c9f8c3
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/soc/intel/cannonlake/romstage/romstage.c | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'src/soc/intel/cannonlake/romstage')

diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index 8b3794f4e9..2673f3700b 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -22,6 +22,7 @@
 #include <console/console.h>
 #include <fsp/util.h>
 #include <intelblocks/cse.h>
+#include <intelblocks/lpc_lib.h>
 #include <intelblocks/pmclib.h>
 #include <memory_info.h>
 #include <soc/iomap.h>
@@ -46,6 +47,8 @@ asmlinkage void car_stage_entry(void)
 	/* initialize Heci interface */
 	heci_init(HECI1_BASE_ADDRESS);
 
+	/* Program LPC generic decoding */
+	pch_enable_lpc();
 	timestamp_add_now(TS_START_ROMSTAGE);
 	s3wake = pmc_fill_power_state(ps) == ACPI_S3;
 	fsp_memory_init(s3wake);
-- 
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