From 81100bf7ff62c4ee53214afb82f2fa9112d109b6 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Fri, 16 Aug 2019 10:37:15 +0300 Subject: soc/intel: Move fill_postcar_frame to memmap.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I84b1fad52d623a879f00c3f721f480f58d7d6d8a Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34894 Reviewed-by: Angel Pons Reviewed-by: David Guckian Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/romstage/romstage.c | 16 ---------------- 1 file changed, 16 deletions(-) (limited to 'src/soc/intel/cannonlake/romstage') diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index fb5e42b200..ba583b9a6e 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include @@ -142,18 +141,3 @@ void mainboard_romstage_entry(void) if (!s3wake) save_dimm_info(); } - -void fill_postcar_frame(struct postcar_frame *pcf) -{ - uintptr_t top_of_ram; - /* - * We need to make sure ramstage will be run cached. At this - * point exact location of ramstage in cbmem is not known. - * Instruct postcar to cache 16 megs under cbmem top which is - * a safe bet to cover ramstage. - */ - top_of_ram = (uintptr_t) cbmem_top(); - printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); - top_of_ram -= 16*MiB; - postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); -} -- cgit v1.2.3