From 6527b1acc7a020e1f0594a7ea30daed0978dd5fd Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 29 Jan 2019 11:04:25 +0530 Subject: soc/intel/cannonlake: Add Whiskeylake SoC kconfig This patch performs below tasks 1. Create SOC_INTEL_COMMON_CANNONLAKE_BASE kconfig. 2. Allow required SoC to select this kconfig to extend CANNONLAKE SoC support and add incremental changes. 3. Select correct SoC support for hatch, sarien, cflrvps and whlrvp. * Hatch is WHL SoC based board * Sarien is WHL SoC based board * CFLRVP U/8/11 are CFL SoC based board * WHLRVP is based on WHL SoC 4. Add correct FSP blobs path for WHL SoC based designs. Change-Id: I66b63361841f5a16615ddce4225c4f6182eabdb3 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/31133 Tested-by: build bot (Jenkins) Reviewed-by: Aamir Bohra Reviewed-by: Furquan Shaikh --- src/soc/intel/cannonlake/romstage/fsp_params.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/intel/cannonlake/romstage') diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index bdaa4afaf1..b8b2c1798c 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -53,7 +53,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) m_cfg->VmxEnable = 0; else m_cfg->VmxEnable = config->VmxEnable; -#if IS_ENABLED(CONFIG_SOC_INTEL_COFFEELAKE) +#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_CANNONLAKE_BASE) m_cfg->SkipMpInit = !chip_get_fsp_mp_init(); #endif -- cgit v1.2.3