From 490546f191cf2aa1aceec97b7d0503f4fb4408f4 Mon Sep 17 00:00:00 2001 From: Michael Niewöhner Date: Tue, 15 Sep 2020 12:20:08 +0200 Subject: soc/intel: rename get_prmrr_size MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit get_prmrr_size does not return the actual PRMRR size but a valid PRMRR size with repect to the users choice in Kconfig. Thus, rename it from `get_prmrr_size` to `get_valid_prmrr_size` to avoid confusion about what it does. Also fix the broken comment in cpulib.h. Change-Id: Id243be50acb741f2c3118ddde082743d08983a53 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/45414 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/cannonlake/romstage/fsp_params.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/intel/cannonlake/romstage') diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index ac42e0054a..3cd148bc0f 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -52,7 +52,7 @@ static void soc_memory_init_params(FSPM_UPD *mupd, const config_t *config) mask |= (1 << i); } m_cfg->PcieRpEnableMask = mask; - m_cfg->PrmrrSize = get_prmrr_size(); + m_cfg->PrmrrSize = get_valid_prmrr_size(); m_cfg->EnableC6Dram = config->enable_c6dram; #if CONFIG(SOC_INTEL_COMETLAKE) m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; -- cgit v1.2.3