From 3ef74493928fafa2955e3b0acecb2b625f223d83 Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Thu, 6 Dec 2018 17:29:55 -0800 Subject: soc/intel/cannonlake: Auto turn on HDA controller Update HDAenable bit in Fsp memory init UPD data base on devicetree settings. BUG=N/A TEST=N/A Change-Id: I5159c00a855a2a9516714ccee8ee9933465c5063 Signed-off-by: Lijian Zhao Reviewed-on: https://review.coreboot.org/c/30097 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie --- src/soc/intel/cannonlake/romstage/fsp_params.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/soc/intel/cannonlake/romstage') diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 3e0f92249a..c3a2509063 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -59,6 +59,14 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) m_cfg->PchIshEnable = 0; else m_cfg->PchIshEnable = dev->enabled; + + /* If HDA is enabled, enable HDA elements */ + dev = dev_find_slot(0, PCH_DEVFN_HDA); + if (!dev) + m_cfg->PchHdaEnable = 0; + else + m_cfg->PchHdaEnable = dev->enabled; + } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -- cgit v1.2.3