From 2973d1e4783a24246292b58b3e9b7ee6aef1222d Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Fri, 17 May 2019 12:31:51 +0530 Subject: vendorcode/intel/fsp/fsp2_0/cometlake: Update FSP-M/S header files as per v1155 This CL implements below changes: 1) Update FSP-M and FSP-S header files as per FSP release version 1155. 2) Update the PcdSerialIoUartNumber reference in fsp_params.c with SerialIoUartDebugControllerNumber. Change-Id: I6d412424f9f5c5d2d56b789c2fef4bdb817a3019 Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/32844 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/romstage/fsp_params.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/soc/intel/cannonlake/romstage') diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 6e492bb73a..77bad8f627 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -50,7 +50,11 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) m_cfg->PcieRpEnableMask = mask; m_cfg->PrmrrSize = config->PrmrrSize; m_cfg->EnableC6Dram = config->enable_c6dram; +#if CONFIG(SOC_INTEL_COMETLAKE) + m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; +#else m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE; +#endif /* * PcdDebugInterfaceFlags * This config will allow coreboot to pass information to the FSP -- cgit v1.2.3