From 26be35a50720f7dc60aa6a28dae151b47cb782ce Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Tue, 17 Apr 2018 16:13:39 -0700 Subject: soc/intel/cannonlake: Set DISB after Dram init DRAM Initialization Scratchpad Bit needs to be set after Dram Initialization finished, according to Cannonlake PCH-LP EDS(#565870) chapter 5.3.1. BUG=None Change-Id: I16dd3787cb743bc5b7492042f3c3757534e1a51c Signed-off-by: Lijian Zhao Reviewed-on: https://review.coreboot.org/25704 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Kin Wai Ng --- src/soc/intel/cannonlake/romstage/romstage.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/cannonlake/romstage') diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index dc9652689a..c8cb927078 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -123,6 +123,7 @@ asmlinkage void car_stage_entry(void) timestamp_add_now(TS_START_ROMSTAGE); s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); + pmc_set_disb(); if (!s3wake) save_dimm_info(); if (postcar_frame_init(&pcf, 1 * KiB)) -- cgit v1.2.3