From 25b387a50b25ceaaca29cf94eb02582a0d0e390a Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Thu, 8 Nov 2018 15:48:14 -0700 Subject: soc/intel/cannonlake: Remove SmbusEnable Remove the SmbusEnable config option from devicetree and instead use the state of the PCI device to determine if it should be enabled or disabled. Change-Id: Id362009e4c8e91699d1ca9bb3c2614e21cfc462a Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/29552 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/cannonlake/romstage/fsp_params.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'src/soc/intel/cannonlake/romstage') diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 8506214425..8f6fa2ff54 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -66,6 +66,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); + const struct device *smbus = dev_find_slot(0, PCH_DEVFN_SMBUS); assert(dev != NULL); const config_t *config = dev->chip_info; FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; @@ -73,7 +74,10 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) soc_memory_init_params(m_cfg, config); /* Enable SMBus controller based on config */ - m_cfg->SmbusEnable = config->SmbusEnable; + if (!smbus) + m_cfg->SmbusEnable = 0; + else + m_cfg->SmbusEnable = smbus->enabled; /* Set debug probe type */ m_cfg->PlatformDebugConsent = config->DebugConsent; -- cgit v1.2.3