From a7d2f2982364f7b9c0c0410f7ba07e6d6c7aa527 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Sun, 18 Aug 2019 06:55:52 +0300 Subject: intel/car: Use common TS_START_ROMSTAGE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This timestamp also got unintentionally removed from some boards as they were transformed to use common romstage entry. Change-Id: I12be278a674f9a2ea073b170a223c41c7fc01a94 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34970 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/romstage/romstage.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/soc/intel/cannonlake/romstage/romstage.c') diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index 5711c15142..fb5e42b200 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -28,7 +28,6 @@ #include #include #include -#include #include "../chip.h" @@ -137,7 +136,6 @@ void mainboard_romstage_entry(void) /* initialize Heci interface */ heci_init(HECI1_BASE_ADDRESS); - timestamp_add_now(TS_START_ROMSTAGE); s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); pmc_set_disb(); -- cgit v1.2.3